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1. 发明申请

US20160344380A1 SYSTEMS AND METHODS OF PHASE FREQUENCY DETECTION WITH CLOCK EDGE OVERRIDING RESET, EXTENDING DETECTION RANGE, IMPROVEMENT OF CYCLE SLIPPING AND/OR OTHER FEATURES 有权
标题翻译：具有时钟边沿重叠的相位频率检测的系统和方法，扩展检测范围，循环滑动和/或其他特性的改进
公开(公告)号：US20160344380A1
公开(公告)日：2016-11-24
申请号：US15159436
申请日：2016-05-19
申请人： GSI Techonology, Inc.
发明人： Chao-Hung CHANG
IPC分类号： H03K5/26 , H03K19/20
CPC分类号： H03K5/26 , H03D13/004 , H03K19/20
摘要： Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.
摘要翻译：公开了与相位频率检测相关的系统和方法。在一个说明性实现中，相位频率检测（PFD）电路装置可以包括具有设定输入，复位输入和输出的第一电路和第二电路，其中所述设定输入具有比所述复位输入更高的优先级，以及附加电路布置并可操作地耦合以提供PFD电路装置的有利操作。根据一些实施方式，例如，提供了具有时钟边缘覆盖复位特征的系统和方法，延长的检测范围和/或在周期滑动之后减少反向电荷。

2. 发明授权

US09385730B2 Phase-rotating phase locked loop and method of controlling operation thereof 有权
标题翻译：相位旋转锁相环及其控制方法
公开(公告)号：US09385730B2
公开(公告)日：2016-07-05
申请号：US14272975
申请日：2014-05-08
申请人： Samsung Electronics Co., Ltd.
发明人： Junhan Bae , Kee-won Kwon , Kyoungho Kim , Jung Hoon Chun , Youngsoo Sohn , Seok Kim
IPC分类号： H03L7/087 , H03L7/081 , H03L7/085 , H03L7/099 , H03L7/10 , H03L7/107
CPC分类号： H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
摘要： A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
摘要翻译：相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。

3. 发明授权

US08995598B2 Low jitter clock recovery circuit 有权
标题翻译：低抖动时钟恢复电路
公开(公告)号：US08995598B2
公开(公告)日：2015-03-31
申请号：US13312773
申请日：2011-12-06
申请人： Carl William Werner
发明人： Carl William Werner
IPC分类号： H03D3/24 , H04L7/033 , H03D13/00 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/091 , H03L7/089
CPC分类号： H04L7/0331 , H03D13/004 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033
摘要： A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
摘要翻译：时钟恢复电路包括用于测量来自压控振荡器（VCO）的第一时钟信号与数据信号之间的相位差的第一相位检测器。基于该相位差响应于控制信号的移相器调整输入时钟信号的相位以产生第二时钟信号。测量第一时钟信号和第二时钟信号之间的相位差，并将所得到的信号进行低通滤波，以得到用于控制VCO的控制信号。包括VCO的锁相环滤除抖动。

4. 发明授权

US08456205B2 Phase-frequency comparator and serial transmission device 失效
标题翻译：相位比较器和串行传输装置
公开(公告)号：US08456205B2
公开(公告)日：2013-06-04
申请号：US12987108
申请日：2011-01-08
申请人： Tatsunori Usugi , Takeshi Isezaki , Takeshi Koyama
发明人： Tatsunori Usugi , Takeshi Isezaki , Takeshi Koyama
IPC分类号： H03L7/06
CPC分类号： H03D13/004
摘要： Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch.
摘要翻译：公开了一种通过简单的电路来稳定环路带宽的相位 - 频率比较器，提供了一个相位 - 频率比较器，它是输入参考时钟和反馈时钟的相位 - 频率比较器，并向上升频率合成器以及向频率合成器提供的向下信号，其提供有第一相位频率比较电路，第二相位比较电路和输入参考时钟和反馈时钟的延迟电路部分，并向第一相位频率比较电路和第二相位比较电路的输入，其中由第一相位频率比较电路执行频率比较，并且相位比较由第一相位频率比较电路和第二相位比较电路相位比较电路控制锁存器。

5. 发明申请

US20130135011A1 PHASE FREQUENCY DETECTOR CIRCUIT 有权
标题翻译：相位检测电路
公开(公告)号：US20130135011A1
公开(公告)日：2013-05-30
申请号：US13308274
申请日：2011-11-30
申请人： Yen-Jen CHEN , I-Ting LEE , Feng Wei KUO , Huan-Neng CHEN , Chewn-Pu JOU
发明人： Yen-Jen CHEN , I-Ting LEE , Feng Wei KUO , Huan-Neng CHEN , Chewn-Pu JOU
IPC分类号： H03D13/00 , H03L7/00
CPC分类号： H03D13/00 , H03D13/004 , H03L7/087 , H03L7/089 , H03L7/10
摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.
摘要翻译：相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。边缘检测器电路被配置为接收第一输入信号和第二输入信号。判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

6. 发明授权

US08433023B2 Method and apparatus for generating a phase dependent control signal 失效
标题翻译：用于产生相位相关控制信号的方法和装置
公开(公告)号：US08433023B2
公开(公告)日：2013-04-30
申请号：US13354702
申请日：2012-01-20
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H03D3/24 , H03L7/06 , G06F1/04
CPC分类号： G11C7/1072 , G11C7/222 , H03D13/004 , H03K5/131 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0812 , H03L7/085 , H03L7/087 , H03L7/0896
摘要： A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The delay value of a voltage-controlled delay circuit and the phase relationship between the first and second clock signals to a predetermined phase relationship are thereby adjusted.
摘要翻译：一种具有相位检测器的计算机系统，其根据第一和第二时钟信号之间的相位关系产生相位相关的控制信号。相位检测器包括接收第一和第二时钟信号的第一和第二相位检测器电路，并产生具有对应于第一和第二时钟信号的时钟沿之间的相位关系的占空比的选择信号。相位检测器还包括电荷泵，其在相位检测器电路接收选择信号，并且当第一和第二时钟信号不具有预定的相位关系时产生增加或减小的控制信号，当第一和第二时钟信号不具有预定的相位关系时，并且第二时钟信号具有预定的相位关系。由此调整压控延迟电路的延迟值和第一和第二时钟信号之间的相位关系到预定的相位关系。

7. 发明申请

US20110103525A1 PULSE SIGNAL WAVEFORM ASYMMETRY IDENTIFICATION UTILIZING SYMBOLIC DYNAMICS 有权
标题翻译：脉冲信号波形不对称识别使用符号动力学
公开(公告)号：US20110103525A1
公开(公告)日：2011-05-05
申请号：US13004020
申请日：2011-01-10
申请人： Lester F. Ludwig
发明人： Lester F. Ludwig
IPC分类号： H04L27/06
CPC分类号： H03D13/004
摘要： A method for identifying asymmetry in a pulse signal is disclosed. An asymmetrical condition is when the time interval of a first input pulse signal having a first value is longer than the time of a second input pulse signal having a second value. Identifying asymmetry includes receiving and detecting the instantaneous signal values of first and second input pulse signals, and associating a unique state symbol with each distinct pair of instantaneous signal values thereby producing a sequence of state symbols. A sequence of state symbols of a first type, a second type, and a third type is identified and associated with a distinct enveloping event pattern. A macroscopic behavioral signature pattern indicating an asymmetrical condition is identified when a first symmetry event symbol of a first kind is followed by a first interval having no identified symmetry event symbol, a second symmetry event symbol of a second kind, and a second interval having no identified symmetry event symbol.
摘要翻译：公开了一种用于识别脉冲信号中的不对称的方法。不对称条件是当具有第一值的第一输入脉冲信号的时间间隔长于具有第二值的第二输入脉冲信号的时间时。识别不对称包括接收和检测第一和第二输入脉冲信号的瞬时信号值，并且将唯一状态符号与每个不同的瞬时信号值对相关联，从而产生状态符号序列。识别第一类型，第二类型和第三类型的状态符号序列并与不同的包络事件模式相关联。当第一种类型的第一对称事件符号之后是没有识别的对称事件符号的第一间隔，第二种类型的第二对称事件符号和没有第二类型的第二间隔时，识别指示不对称条件的宏观行为签名模式确定对称事件符号。

8. 发明授权

US07697652B2 Recovery of clock and data using quadrature clock signals 有权
标题翻译：使用正交时钟信号恢复时钟和数据
公开(公告)号：US07697652B2
公开(公告)日：2010-04-13
申请号：US10779677
申请日：2004-02-18
申请人： Dae-Seung Jeong , Ueda Kimio
发明人： Dae-Seung Jeong , Ueda Kimio
IPC分类号： H03D3/24
CPC分类号： H03D13/004
摘要： A quarter-rate phase detector can include: four latches controllable to latch, at different times according to quadrature clock signals, respectively, data received by the phase detector so as to form latched signals; an error circuit to combine corresponding ones of the latched signals, respectively, resulting in a plurality of intermediate signals; and a multiplexing unit to selectively output the intermediate signals as a phase error signal. A related method can have similar features.
摘要翻译：四分之一速率相位检测器可以包括：四个锁存器，可分别根据正交时钟信号在不同时间锁存由相位检测器接收的数据，以形成锁存信号; 分别组合相应的锁存信号的误差电路，产生多个中间信号; 以及复用单元，用于选择性地输出中间信号作为相位误差信号。相关方法可以具有相似的特征。

9. 发明授权

US07622960B2 Metastable-resistant phase comparing circuit 有权
标题翻译：耐转移相位比较电路
公开(公告)号：US07622960B2
公开(公告)日：2009-11-24
申请号：US12073409
申请日：2008-03-05
申请人： Yasuhiro Takai
发明人： Yasuhiro Takai
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03D13/004
摘要： A phase comparing circuit includes a first storage circuit for reading an external clock signal based on a control clock signal; first and second inverters for inverting a signal from the first storage circuit based respectively on first and second threshold levels; third and fourth inverters for inverting respective signals output from the first and second inverters; a delay circuit for delaying the control clock signal by a specific time; a coincidence control circuit for setting the delayed control clock signal to be active when the signals from the third and fourth inverters coincide with each other, and setting it to be inactive when the signals from the third and fourth inverters do not coincide with each other; and a second storage circuit for reading a signal output form the first storage circuit when the delayed control clock signal is active, and outputting the read signal as the control signal.
摘要翻译：相位比较电路包括：第一存储电路，用于基于控制时钟信号读取外部时钟信号; 第一和第二反相器，用于分别基于第一和第二阈值电平反转来自第一存储电路的信号; 第三和第四反相器，用于反转从第一和第二反相器输出的各个信号; 用于将控制时钟信号延迟特定时间的延迟电路; 当来自第三和第四变换器的信号彼此一致时，将延迟的控制时钟信号设置为有效的一致控制电路，并且当来自第三和第四变换器的信号彼此不一致时将其设置为不活动; 以及第二存储电路，用于当延迟的控制时钟信号有效时，读取从第一存储电路输出的信号，并输出读取的信号作为控制信号。

10. 发明授权

US07532038B2 Phase detecting circuit having adjustable gain curve and method thereof 有权
标题翻译：具有可调增益曲线的相位检测电路及其方法
公开(公告)号：US07532038B2
公开(公告)日：2009-05-12
申请号：US11477918
申请日：2006-06-30
申请人： Joanna Lin
发明人： Joanna Lin
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03D13/004
摘要： A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit. The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control signals. The clock signals have the same frequency but different phases, and the frequency of the data signal is a multiple of the frequency of the clock signals. The logic circuit performs various logic operations according to these control signals to output at least one set of gain control signals for adjusting a gain curve of the phase detecting circuit.
摘要翻译：具有可调增益曲线的相位检测电路包括多个相位检测器和逻辑电路。相位检测器通过比较来检测数据信号和多个时钟信号之间的相位差，以输出多个控制信号。时钟信号具有相同的频率但不同的相位，数据信号的频率是时钟信号频率的倍数。逻辑电路根据这些控制信号执行各种逻辑运算，以输出至少一组用于调整相位检测电路的增益曲线的增益控制信号。

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