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1. 发明授权

US06181705B2 System and method for management a communications buffer 失效
标题翻译：用于管理通信缓冲区的系统和方法
公开(公告)号：US06181705B2
公开(公告)日：2001-01-30
申请号：US08691803
申请日：1996-08-14
申请人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
发明人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
IPC分类号： H04L1308
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9052
摘要： A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.
摘要翻译：网络缓冲存储器被划分为包括多个小节连续部分和多个巨型图连续部分的位置池。可用于存储数据包的tinygram连续区段列在tinygram指针列表中。可用于存储数据包的巨型连续段也列在巨型指针列表中。用于将分组区分为微小图形和巨型图形的阈值被编程。当接收到数据包时，将根据阈值进行测量。响应于在到达阈值之前检测到分组状态的结束，将分组存储在微小的连续部分中。否则，数据包存储在巨型图连续部分。部分的可用性是通过查询指针的FIFO列表来确定的。

2. 发明授权

US06765911B1 Communications adapter for implementing communications in a network and providing multiple modes of communications 失效
标题翻译：用于在网络中实现通信并提供多种通信模式的通信适配器
公开(公告)号：US06765911B1
公开(公告)日：2004-07-20
申请号：US09243858
申请日：1999-02-03
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
IPC分类号： H04L1256
CPC分类号： H04L47/58 , H04L12/5601 , H04L47/50 , H04L2012/5652 , H04L2012/5679
摘要： A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.
摘要翻译：提供了一种用于在通信网络中实现通信的方法和装置。用于实现通信的装置包括到通信网络的系统接口。调度器调度入队单元和要发送的入队帧。分段器将帧和小区划分成应用于媒体适配块的小区或帧，以在多个模式中选择的一个模式中进行传输。

3. 发明授权

US06498782B1 Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation 有权
标题翻译：通信方式和千兆以太网通信适配器提供服务质量和接收机连接速度差异化
公开(公告)号：US06498782B1
公开(公告)日：2002-12-24
申请号：US09243956
申请日：1999-02-03
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
IPC分类号： G06F1100
CPC分类号： H04L47/24 , H04L12/40032 , H04L12/4015 , H04L12/413 , H04L47/10 , H04L47/22 , H04L47/50 , H04L47/568 , H04L47/6215
摘要： A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.
摘要翻译：提供了一种用于实现通信网络中的通信的方法和千兆以太网通信适配器。定义要发送的数据的传输队列。为传输队列设置传输速率。要发送的数据在传输队列中排队。传输队列可以被划分为多个优先级队列，例如使用时轮，并为每个传输队列设置一个传输速率。

4. 发明授权

US5706461A Method and apparatus for implementing virtual memory having multiple selected page sizes 失效
公开(公告)号：US5706461A
公开(公告)日：1998-01-06
申请号：US638223
申请日：1996-04-26
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Kevin Gerard Plotz , Fadi-Christian E. Safi , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Kevin Gerard Plotz , Fadi-Christian E. Safi , Albert Alfonse Slane
IPC分类号： G06F12/02 , G06F12/10 , G11B25/04 , G11B33/12 , G06F12/00 , G06F12/04
CPC分类号： G06F12/10 , G06F12/1009 , G11B25/043 , G06F12/0292 , G06F2212/652 , G11B33/12
摘要： A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.

5. 发明授权

US06823502B2 Placement of configurable input/output buffer structures during design of integrated circuits 失效
标题翻译：在集成电路设计期间配置输入/输出缓冲结构
公开(公告)号：US06823502B2
公开(公告)日：2004-11-23
申请号：US10334568
申请日：2002-12-31
申请人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
发明人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.
摘要翻译：考虑到产品的扩散可配置I / O块和/或I / O硬件的要求，用于设计集成电路和半导体产品的工具，为I / O缓冲结构生成正确的RTL。给定部分制造的半导体产品的切片描述，设计者可以生成应用集的I / O资源。然后给出具有晶体管结构以及扩散的可配置I / O块和/或I / O硬件以及多个伴随壳的应用组，这里的I / O生成工具自动读取具有切片描述的数据库和从晶体管结构生成I / O缓冲结构。 I / O生成工具进一步调整并集成了具有自己的逻辑的客户的两个或两个客户的输入，并且请求特定的半导体产品或者从它们的预先建立的逻辑获得IP核。 I / O生成工具可以从晶体管结构创建正确的RTL，以正确布局，定时，测试和半导体产品的I / O缓冲放大器的功能，无论是增量还是全局。一旦创建了I / O缓冲区结构，它们就被多个shell限定，包括验证shell，静态时序分析shell，制造测试shell和RTL分析shell。

6. 发明授权

US5761716A Rate based memory replacement mechanism for replacing cache entries when the cache is full 失效
标题翻译：基于速率的内存替换机制，用于在缓存已满时替换缓存条目
公开(公告)号：US5761716A
公开(公告)日：1998-06-02
申请号：US640605
申请日：1996-05-01
申请人： Jonathan William Byrn , Gary Scott Delp , Kevin Gerard Plotz
发明人： Jonathan William Byrn , Gary Scott Delp , Kevin Gerard Plotz
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/121
摘要： A rate based mechanism for determining which data to replace in a cache when the cache is full. The computer system processes data, which are associated with multiple channels or processes. These channels or processes have different, cyclic rates. When the cache is full, the system chooses the data to replace by selecting the data block in the cache that has the lowest rate and is the most recently used.
摘要翻译：一种基于速率的机制，用于在高速缓存已满时确定要在高速缓存中替换的数据。计算机系统处理与多个通道或过程相关联的数据。这些通道或过程具有不同的循环速率。当缓存已满时，系统通过选择具有最低速率且最近使用的缓存中的数据块来选择要替换的数据。

7. 发明授权

US07430725B2 Suite of tools to design integrated circuits 失效
标题翻译：套件设计集成电路的工具
公开(公告)号：US07430725B2
公开(公告)日：2008-09-30
申请号：US11156319
申请日：2005-06-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
摘要翻译：本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。这些设计经过其他工具的合格，测试和验证。这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。这些工具也具有迭代模式和全局模式。在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。这套生成工具生成设计视图，包括用于制造铸造的合格网表。

8. 发明授权

US07055113B2 Simplified process to design integrated circuits 有权
标题翻译：集成电路设计简化过程
公开(公告)号：US07055113B2
公开(公告)日：2006-05-30
申请号：US10335360
申请日：2002-12-31
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
摘要翻译：本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。这些设计经过其他工具的合格，测试和验证。这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。这些工具也具有迭代模式和全局模式。在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。这套生成工具生成设计视图，包括用于制造铸造的合格网表。

9. 发明授权

US06910201B2 Custom clock interconnects on a standardized silicon platform 失效
公开(公告)号：US06910201B2
公开(公告)日：2005-06-21
申请号：US10664137
申请日：2003-09-17
申请人： Jonathan William Byrn , James Arnold Jensen , Matthew Scott Wingren
发明人： Jonathan William Byrn , James Arnold Jensen , Matthew Scott Wingren
IPC分类号： G06F17/50 , H01L27/02 , H01L27/10 , H02H3/00
CPC分类号： G06F17/5045 , H01L27/0203
摘要： A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

10. 发明授权

US06289430B1 Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags 失效
标题翻译：在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置
公开(公告)号：US06289430B1
公开(公告)日：2001-09-11
申请号：US09251029
申请日：1999-02-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
IPC分类号： G06F1210
CPC分类号： G06F12/0875 , G06F12/0292
摘要： A method and apparatus are provided for target addressing and translation in a non-uniform memory environment with user defined target tags. The apparatus for target addressing and translation includes a processor and a first address translation unit coupled to the processor. The first address translation unit translates an effective address (EA) to a real address (RA). The first address translation unit includes a target tag associated with each address translation. A second address translation unit translates a real address (RA) to a target address (TA). The second address translation unit includes a target tag associated with each address translation. A cache includes a cache directory and a target tag is stored into the cache directory with each cache fill.
摘要翻译：提供了一种用于在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置。用于目标寻址和转换的装置包括耦合到处理器的处理器和第一地址转换单元。第一地址翻译单元将有效地址（EA）转换为实际地址（RA）。第一地址转换单元包括与每个地址转换相关联的目标标签。第二地址转换单元将实际地址（RA）转换为目标地址（TA）。第二地址转换单元包括与每个地址转换相关联的目标标签。高速缓存包括缓存目录，并且目标标签被存储到每个缓存填充的高速缓存目录中。

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