专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06910201B2 Custom clock interconnects on a standardized silicon platform 失效
公开(公告)号：US06910201B2
公开(公告)日：2005-06-21
申请号：US10664137
申请日：2003-09-17
申请人： Jonathan William Byrn , James Arnold Jensen , Matthew Scott Wingren
发明人： Jonathan William Byrn , James Arnold Jensen , Matthew Scott Wingren
IPC分类号： G06F17/50 , H01L27/02 , H01L27/10 , H02H3/00
CPC分类号： G06F17/5045 , H01L27/0203
摘要： A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

2. 发明授权

US06823502B2 Placement of configurable input/output buffer structures during design of integrated circuits 失效
标题翻译：在集成电路设计期间配置输入/输出缓冲结构
公开(公告)号：US06823502B2
公开(公告)日：2004-11-23
申请号：US10334568
申请日：2002-12-31
申请人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
发明人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.
摘要翻译：考虑到产品的扩散可配置I / O块和/或I / O硬件的要求，用于设计集成电路和半导体产品的工具，为I / O缓冲结构生成正确的RTL。给定部分制造的半导体产品的切片描述，设计者可以生成应用集的I / O资源。然后给出具有晶体管结构以及扩散的可配置I / O块和/或I / O硬件以及多个伴随壳的应用组，这里的I / O生成工具自动读取具有切片描述的数据库和从晶体管结构生成I / O缓冲结构。 I / O生成工具进一步调整并集成了具有自己的逻辑的客户的两个或两个客户的输入，并且请求特定的半导体产品或者从它们的预先建立的逻辑获得IP核。 I / O生成工具可以从晶体管结构创建正确的RTL，以正确布局，定时，测试和半导体产品的I / O缓冲放大器的功能，无论是增量还是全局。一旦创建了I / O缓冲区结构，它们就被多个shell限定，包括验证shell，静态时序分析shell，制造测试shell和RTL分析shell。

3. 发明授权

US07430725B2 Suite of tools to design integrated circuits 失效
标题翻译：套件设计集成电路的工具
公开(公告)号：US07430725B2
公开(公告)日：2008-09-30
申请号：US11156319
申请日：2005-06-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
摘要翻译：本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。这些设计经过其他工具的合格，测试和验证。这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。这些工具也具有迭代模式和全局模式。在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。这套生成工具生成设计视图，包括用于制造铸造的合格网表。

4. 发明授权

US07055113B2 Simplified process to design integrated circuits 有权
标题翻译：集成电路设计简化过程
公开(公告)号：US07055113B2
公开(公告)日：2006-05-30
申请号：US10335360
申请日：2002-12-31
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
摘要翻译：本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。这些设计经过其他工具的合格，测试和验证。这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。这些工具也具有迭代模式和全局模式。在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。这套生成工具生成设计视图，包括用于制造铸造的合格网表。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式