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1. 发明授权

US5116778A Dopant sources for CMOS device 失效
标题翻译： CMOS器件的掺铒光源
公开(公告)号：US5116778A
公开(公告)日：1992-05-26
申请号：US474614
申请日：1990-02-05
申请人： Jacob D. Haskell , Steven C. Avanzino , Balaji Swaminathan
发明人： Jacob D. Haskell , Steven C. Avanzino , Balaji Swaminathan
IPC分类号： H01L21/22 , H01L21/225 , H01L21/316 , H01L21/74 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/022 , H01L21/2255 , H01L21/31625 , H01L21/743 , H01L21/762 , H01L21/76229 , H01L21/76237 , H01L21/823878
摘要： A process is provided for doping both sidewalls (26, 28) of isolation trenches (24, 26, 28) and connector regions (46, 48) between sources (58) and gate areas (62) and between drains (60) and gate areas in silicon CMOS devices. Appropriately doped glasses (16, 18, 30) formed on the silicon substrate (14) serve as the source of doping.

2. 发明授权

US4962064A Method of planarization of topologies in integrated circuit structures 失效
标题翻译：集成电路结构拓扑的平面化方法
公开(公告)号：US4962064A
公开(公告)日：1990-10-09
申请号：US193478
申请日：1988-05-12
申请人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
发明人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/321 , H01L21/76 , H01L21/762
CPC分类号： H01L21/3212 , H01L21/31056 , H01L21/76229 , Y10S148/051 , Y10S438/959
摘要： A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying integrated circuit structure to provide the desired highly planarized structure.

3. 发明授权

US4954459A Method of planarization of topologies in integrated circuit structures 失效
标题翻译：集成电路结构拓扑的平面化方法
公开(公告)号：US4954459A
公开(公告)日：1990-09-04
申请号：US376176
申请日：1989-07-03
申请人： Steven C. Avanzino , Jacob D. Haskell
发明人： Steven C. Avanzino , Jacob D. Haskell
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/3205 , H01L21/321 , H01L21/762
CPC分类号： H01L21/3212 , H01L21/31056 , H01L21/76229 , Y10S148/051 , Y10S438/959
摘要： A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to form a highly planarized structure. Optionally, the oxide layer may be further etched anisotropically until the upper surfaces of the underlying integrated circuit structure is exposed.
摘要翻译：公开了一种用于制造具有平坦化到集成电路结构的相邻部分的平面的沉积氧化物部分的高度平坦化的集成电路结构的方法，其包括：在集成电路结构上沉积，该集成电路结构具有高于其余部分的高度的第一部分集成电路结构，具有超过所述集成电路结构的其余部分之上的所述第一部分的高度的厚度的共形氧化物层; 在其上具有一个或多个开口的所述沉积的氧化物层上形成图案化掩模层，与所述集成电路结构的较高高度的第一部分对齐; 将所述保形氧化物层的暴露部分通过所述掩模开口蚀刻到约等于所述共形氧化物层的未曝光部分的水平的水平; 去除掩模层; 并抛光氧化物层以除去在蚀刻步骤之后残留的保形氧化物层的凸起部分，以形成高度平坦化的结构。任选地，可以进一步各向异性地蚀刻氧化物层，直到暴露底层集成电路结构的上表面。

4. 发明授权

US07157795B1 Composite tantalum nitride/tantalum copper capping layer 有权
标题翻译：复合氮化钽/钽铜覆盖层
公开(公告)号：US07157795B1
公开(公告)日：2007-01-02
申请号：US10934511
申请日：2004-09-07
申请人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
发明人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L21/76849 , Y10S438/927
摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.
摘要翻译：通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

5. 发明授权

US07148144B1 Method of forming copper sulfide layer over substrate 有权
标题翻译：在基材上形成硫化铜层的方法
公开(公告)号：US07148144B1
公开(公告)日：2006-12-12
申请号：US10939897
申请日：2004-09-13
申请人： Steven C. Avanzino
发明人： Steven C. Avanzino
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , C01G3/12 , C23C16/0218 , C23C16/305
摘要： Methods of forming copper sulfide regions or layers over a substrate are disclosed. The copper sulfide regions or layers are formed by contacting a sulfide compound with a substrate containing at least copper and contacting a copper vapor precursor with the substrate to form the copper sulfide layer. Methods of making a memory devices/cells containing a copper sulfide layer, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
摘要翻译：公开了在衬底上形成硫化铜区域或层的方法。通过使硫化物化合物与至少含有铜的基材接触并使铜蒸气前体与基材接触而形成硫化铜层而形成硫化铜区域。还公开了制造含有硫化铜层的存储器件/单元的方法，使用存储器件/单元的方法，以及诸如包含存储器件/单元的计算机的器件。

6. 发明授权

US07011762B1 Metal bridging monitor for etch and CMP endpoint detection 失效
标题翻译：用于蚀刻和CMP端点检测的金属桥接监视器
公开(公告)号：US07011762B1
公开(公告)日：2006-03-14
申请号：US10419534
申请日：2003-04-21
申请人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
发明人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
IPC分类号： C23F1/00 , G01R31/00
CPC分类号： H01L21/3212 , H01L21/32051 , H01L21/32136 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
摘要翻译：本发明的一个方面涉及包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层和至少一个嵌入在晶片内和晶片中的至少一个的电传感器，以便于金属的实时监测当它通过减色金属化过程进行时。本发明的另一方面涉及一种用于实时监测减色金属化过程以便在持续过程中实现立即响应的系统和方法。该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动从电传感器检测和接收，用于实时监测减色金属化处理。

7. 发明授权

US06562185B2 Wafer based temperature sensors for characterizing chemical mechanical polishing processes 有权
标题翻译：用于表征化学机械抛光工艺的基于晶圆的温度传感器
公开(公告)号：US06562185B2
公开(公告)日：2003-05-13
申请号：US09955552
申请日：2001-09-18
申请人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： B24B3700
CPC分类号： B24B37/015
摘要： A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.
摘要翻译：提供了表征化学机械抛光工艺的系统。该系统包括具有位于金属，多晶硅和/或电介质层和/或衬底中和/或上的金属，多晶硅和/或电介质层和/或衬底和温度传感器的晶片。该系统还包括一个温度监控系统，可以从温度传感器读取晶圆温度，并且可以分析晶圆温度以表征化学机械抛光过程。这种表征包括产生关于晶片温度和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。这些关系与晶片温度相关，如与抛光时间，压力，速度，浆料性质和晶片/金属层性质等参数相关。可以采用这种表征，例如，更好地理解CMP工艺，以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备。

8. 发明授权

US06530997B1 Use of gaseous silicon hydrides as a reducing agent to remove re-sputtered silicon oxide 有权
标题翻译：使用气态氢化硅作为还原剂去除重新溅射的氧化硅
公开(公告)号：US06530997B1
公开(公告)日：2003-03-11
申请号：US09543484
申请日：2000-04-06
申请人： Steven C. Avanzino , Larry Yu Wang
发明人： Steven C. Avanzino , Larry Yu Wang
IPC分类号： B08B704
CPC分类号： C23C14/022
摘要： A method and article of manufacture of a semiconductor device having a cleaned source/drain surface and substantially uniform cobalt silicide deposited thereon. The method of the invention includes a precursor conventional step of an argon ion pre-sputter step which generally cleans the semiconductor device surfaces but ensures a resputtering of SiO2 to form SiOx species deposits on the source/drain surface of the device. An in situ treatment using silicon hydride species causes reduction of the SiOx species leaving a cleaned residual silicon which can accept a cobalt deposition to form a desired cobalt silicide layer on the source/drain surface.
摘要翻译：具有清洁的源极/漏极表面和沉积在其上的基本均匀的硅化钴的半导体器件的方法和制品。本发明的方法包括氩离子预溅射步骤的前体常规步骤，其通常清洁半导体器件表面，但是确保SiO 2的再溅射以在器件的源极/漏极表面上形成SiO x物质沉积物。使用硅氢化物物质的原位处理导致SiO x物质的还原，留下清洁的剩余硅，其可以接受钴沉积以在源极/漏极表面上形成期望的钴硅化物层。

9. 发明授权

US06469385B1 Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers 有权
标题翻译：集成电路与介质扩散阻挡层形成在互连和层间电介质层之间
公开(公告)号：US06469385B1
公开(公告)日：2002-10-22
申请号：US09874175
申请日：2001-06-04
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L23522
CPC分类号： H01L23/5329 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76841 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的电介质层具有设置在其中的开口。电介质层是能够改变为阻挡介电材料的非阻挡介电材料。开口周围的电介质层变成阻挡电介质材料，并且沉积导体芯材以填充开口。处理导体芯以形成用于集成电路的通道。

10. 发明授权

US06454916B1 Selective electroplating with direct contact chemical polishing 失效
标题翻译：选择性电镀与直接接触化学抛光
公开(公告)号：US06454916B1
公开(公告)日：2002-09-24
申请号：US09477810
申请日：2000-01-05
申请人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
发明人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
IPC分类号： C25D1700
CPC分类号： C25D5/22 , B23H5/08 , C25D7/12 , C25D17/001
摘要： A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.
摘要翻译：沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。电镀材料填充图案化到半导体晶片的衬底中的凹槽，但是由于扩散器的接触和旋转，防止了在半导体晶片的顶表面上形成很大程度。由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上，所以化学机械抛光（CMP）平面化被显着地减少或完全消除。

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