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1. 发明授权

US09287186B2 Method and structure for determining thermal cycle reliability 有权
公开(公告)号：US09287186B2
公开(公告)日：2016-03-15
申请号：US12128260
申请日：2008-05-28
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58 , H01L21/66 , H01L23/522 , H01L23/00 , H05K1/09 , H05K1/02
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

2. 发明申请

US20120248608A1 SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS OF MAKING SAME 有权
标题翻译：自成型，后端互连的自对准障碍及其制造方法
公开(公告)号：US20120248608A1
公开(公告)日：2012-10-04
申请号：US13078683
申请日：2011-04-01
申请人： Hui Jae Yoo , Jeffery D. Bielefeld , Sean W. King , Sridhar Balakrishnan
发明人： Hui Jae Yoo , Jeffery D. Bielefeld , Sean W. King , Sridhar Balakrishnan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/2855 , H01L21/32053 , H01L21/76832 , H01L21/76835 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76867 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.
摘要翻译：在后端金属化的层间电介质层（ILD）中形成绝缘线的工艺包括在使阻挡前体中的至少一个合金元素引起的金属屏障前体之间形成电介质势垒 ILD。因此，介电阻挡层是自形成的自对准势垒。热处理在使至少一种合金元素从其较高浓度的区域迁移到其较低浓度的区域的条件下进行以进一步形成电介质阻挡层。通过该方法制造各种装置。

3. 发明授权

US08034709B2 Method for forming composite barrier layer 有权
标题翻译：形成复合阻挡层的方法
公开(公告)号：US08034709B2
公开(公告)日：2011-10-11
申请号：US12287516
申请日：2008-10-10
申请人： Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
发明人： Cheng-Lin Huang , Ching-Hua Hsieh , Hsien-Ming Lee , Shing-Chyang Pan , Chao-Hsien Peng , Li-Lin Su , Jing-Cheng Lin , Shao-Lin Shue , Mong-Song Liang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76846 , H01L21/76862 , Y10S438/927
摘要： Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.
摘要翻译：提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种介电材料和导电材料具有优异的粘合性能。复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。

4. 发明授权

US07759712B2 Solid-state imaging device, solid-state imaging apparatus and methods for manufacturing the same 有权
标题翻译：固态成像装置，固态成像装置及其制造方法
公开(公告)号：US07759712B2
公开(公告)日：2010-07-20
申请号：US11607756
申请日：2006-11-30
申请人： Ikuhiro Yamamura
发明人： Ikuhiro Yamamura
IPC分类号： H01L31/062
CPC分类号： H01L27/14636 , H01L27/1462 , H01L27/14623 , Y10S438/927
摘要： To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.
摘要翻译：为了配置用于抑制不在光接收单元2上或上方的区域中的布线材料的扩散的扩散抑制膜5a，5b和5c，形成在上述区域上方的扩散抑制膜5a，5b，5c 光接收单元2被选择性地去除。或者，扩散抑制膜仅布置在布线4a，4b和4c的顶表面上，并且仅在光接收单元上或上方的区域中布置钝化膜12和层间绝缘膜3a，3b和3c 因此，通过不同的绝缘膜之间的界面较少，入射区域的入射光的反射较少，入射光13高效地通过这些绝缘膜并进入光接收单元2.因此，光接收单元2可以接收足够量的入射光13。

5. 发明授权

US07569835B2 Gating grid and method of manufacture 失效
标题翻译：门格栅和制造方法
公开(公告)号：US07569835B2
公开(公告)日：2009-08-04
申请号：US11714691
申请日：2007-03-06
申请人： Brian G. Frederick , Lawrence J. LeGore , Rosemary Smith , Scott Collins , Robert H. Jackson, III
发明人： Brian G. Frederick , Lawrence J. LeGore , Rosemary Smith , Scott Collins , Robert H. Jackson, III
IPC分类号： H01J29/52 , H01J37/063 , G01D59/44 , H01J49/00
CPC分类号： H01J49/061 , Y10S438/927 , Y10S438/977 , Y10T29/49046 , Y10T29/49117
摘要： The present invention relates generally to grids for gating a stream of charged particles and methods for manufacturing the same. In one embodiment, the present invention relates to a Bradbury-Nielson gate having transmission line grid elements. In one embodiment is a feed structure for a gating grid where a drive source is coupled to a feeding transmission line with the same geometry as the chopper and continues with the same geometry to a termination transmission line. Also included is a method for fabricating a gate for charged particles which includes micromachining at least two gate elements from at least one wafer, wherein each gate element includes at least one grid element; metalizing the grid elements; and assembling the gate elements such that the grid elements of the gate elements are interleaved, thereby forming a Bradbury Nielson gate.
摘要翻译：本发明一般涉及用于选通带电粒子流的栅格及其制造方法。在一个实施例中，本发明涉及具有传输线网格元件的Bradbury-Nielson门。在一个实施例中是用于门控格栅的馈送结构，其中驱动源耦合到与斩波器具有相同几何形状的馈电传输线，并且以相同的几何形状连续地连接到终端传输线。还包括一种用于制造带电粒子的栅极的方法，其包括从至少一个晶片微加工至少两个栅极元件，其中每个栅极元件包括至少一个栅格元件; 金属化网格元素; 以及组装门元件，使得门元件的栅格元件交错，从而形成Bradbury Nielson门。

6. 发明授权

US07508082B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07508082B2
公开(公告)日：2009-03-24
申请号：US11844381
申请日：2007-08-24
申请人： Toshiyuki Takewaki , Noriaki Oda
发明人： Toshiyuki Takewaki , Noriaki Oda
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/0401 , H01L2224/05017 , H01L2224/05018 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05571 , H01L2224/05647 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , Y10S438/927 , H01L2924/00014 , H01L2224/05552
摘要： There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.
摘要翻译：提供了一种解决了在焊盘部分中粘附不良的问题，同时抑制焊盘部分的凹陷。形成覆盖绝缘区域并且具有Cu焊盘区域上方的开口的SiON膜，并且在SiON膜的开口中形成阻挡金属膜。这种结构提供了其中Cu焊盘区域和绝缘区域之间的界面的上部被SiON膜覆盖的结构。

7. 发明申请

US20080293257A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
标题翻译：双层封装层互连结构
公开(公告)号：US20080293257A1
公开(公告)日：2008-11-27
申请号：US12186923
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.
摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

8. 发明授权

US07327031B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07327031B2
公开(公告)日：2008-02-05
申请号：US10953454
申请日：2004-09-30
申请人： Toshiyuki Takewaki , Noriaki Oda
发明人： Toshiyuki Takewaki , Noriaki Oda
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/0401 , H01L2224/05017 , H01L2224/05018 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05571 , H01L2224/05647 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , Y10S438/927 , H01L2924/00014 , H01L2224/05552
摘要： There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.
摘要翻译：提供了一种解决了在焊盘部分中粘附不良的问题，同时抑制焊盘部分的凹陷。形成覆盖绝缘区域并且具有Cu焊盘区域上方的开口的SiON膜，并且在SiON膜的开口中形成阻挡金属膜。这种结构提供了其中Cu焊盘区域和绝缘区域之间的界面的上部被SiON膜覆盖的结构。

9. 发明申请

US20070102753A1 Cross diffusion barrier layer in gate structure 审中-公开
标题翻译：栅极结构中的交叉扩散阻挡层
公开(公告)号：US20070102753A1
公开(公告)日：2007-05-10
申请号：US11646896
申请日：2006-12-28
申请人： Sanh Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene Gifford
发明人： Sanh Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene Gifford
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L27/11 , H01L21/823842 , H01L21/823871 , H01L27/1104 , H01L29/4941 , Y10S257/903 , Y10S438/927
摘要： Various embodiments include a substrate having including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate, an insulation layer overlying the substrate, a gate layer overlying the insulation layer, a barrier layer overlying the gate layer, and an electrode layer overlying the barrier layer. The first and third doped regions may be located on a first side of the gate layer. The second and fourth doped regions may be located on a second side of the gate layer. The first and third doped regions may be source and drain regions of a first transistor. The second and fourth doped regions may be source and drain regions of a second transistor. The gate layer may include a gate segment to couple to a third transistor. Other embodiments are disclosed.
摘要翻译：各种实施例包括具有第一掺杂区域和位于衬底第一侧上的第二掺杂区域的衬底，以及位于衬底第二侧上的第三掺杂区域和第四掺杂区域，覆盖衬底的绝缘层，覆盖绝缘层的栅极层，覆盖栅极层的势垒层和覆盖阻挡层的电极层。第一和第三掺杂区域可以位于栅极层的第一侧上。第二和第四掺杂区域可以位于栅极层的第二侧上。第一和第三掺杂区可以是第一晶体管的源区和漏区。第二和第四掺杂区可以是第二晶体管的源区和漏区。栅极层可以包括耦合到第三晶体管的栅极段。公开了其他实施例。

10. 发明申请

US20050206002A1 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
标题翻译：具有镶嵌结构的布线层的半导体器件及其制造方法
公开(公告)号：US20050206002A1
公开(公告)日：2005-09-22
申请号：US11121976
申请日：2005-05-05
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/532 , H01L27/108 , H01L21/4763 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.
摘要翻译：在半导体器件中，在设置在半导体衬底上的氧化硅膜的表面部分中形成布线图案槽。布线层被埋入布线图案槽中，其间插入阻挡金属膜。从布线图形槽的各侧壁部选择性地去除阻挡金属膜。换句话说，阻挡金属膜仅留在布线图案槽的底部。因此，可以在半导体器件中形成具有在布线图案槽的每个侧壁和布线层的每一侧之间的介电常数低的中空部的镶嵌布线层。

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