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1. 发明授权

US06680541B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06680541B2
公开(公告)日：2004-01-20
申请号：US10050859
申请日：2002-01-18
申请人： Takeshi Furusawa , Daisuke Ryuzaki , Noriyuki Sakuma , Shuntaro Machida , Kenji Hinode , Ryou Yoneyama
发明人： Takeshi Furusawa , Daisuke Ryuzaki , Noriyuki Sakuma , Shuntaro Machida , Kenji Hinode , Ryou Yoneyama
IPC分类号： H01L23522
CPC分类号： H01L21/76808 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
摘要翻译：至少含有硅原子，氧原子和碳原子的氧原子与硅原子的数量比为1.5以上，碳原子数与硅原子数之比为1〜2的金属间绝缘膜，具有膜厚收缩率在14％以下的氧化时，介电常数非常低，抗蚀剂蚀刻的选择性高，可以在半导体器件中不使用氧化硅保护膜的情况下使用。

2. 发明授权

US06690084B1 Semiconductor device including insulation film and fabrication method thereof 有权
标题翻译：包括绝缘膜的半导体器件及其制造方法
公开(公告)号：US06690084B1
公开(公告)日：2004-02-10
申请号：US09716334
申请日：2000-11-21
申请人： Hideki Mizuhara , Hiroyuki Watanabe , Naoteru Matsubara
发明人： Hideki Mizuhara , Hiroyuki Watanabe , Naoteru Matsubara
IPC分类号： H01L23522
CPC分类号： H01L21/02126 , H01L21/02129 , H01L21/02137 , H01L21/02282 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/02362 , H01L21/31111 , H01L21/31116 , H01L21/31155 , H01L21/31612 , H01L21/31633 , H01L21/3185 , H01L21/76825 , H01L21/76829
摘要： A semiconductor device including an insulation film superior in insulation characteristic is obtained. Boron ions are introduced by ion implantation into an organic SOG film with a silicon nitride film formed on the organic SOG film. By this boron implantation, the property of the organic SOG film is modified. The moisture and hydroxyl group included in the film are greatly reduced irrespective of the amount of dose of ions. By using such a layered film of a modified SOG film and a silicon nitride film thereupon as an interlayer insulation film or a passivation film, the water resistance of a semiconductor device can be improved sufficiently.
摘要翻译：获得包括绝缘特性优异的绝缘膜的半导体器件。通过离子注入将硼离子引入到在有机SOG膜上形成的氮化硅膜的有机SOG膜中。通过这种硼注入，有机SOG膜的性质被改变。包括在膜中的水分和羟基与离子的剂量无关地大大降低。通过使用这样的改性SOG膜和氮化硅膜的分层膜作为层间绝缘膜或钝化膜，可以充分提高半导体器件的耐水性。

3. 发明授权

US06518676B2 Metal interconnections and active matrix substrate using the same 有权
公开(公告)号：US06518676B2
公开(公告)日：2003-02-11
申请号：US09866121
申请日：2001-05-25
申请人： Yoshimasa Chikama , Yoshihiro Izumi
发明人： Yoshimasa Chikama , Yoshihiro Izumi
IPC分类号： H01L23522
CPC分类号： H01L21/288 , G02F1/136286 , H01J2211/46 , H01L21/2885 , H01L21/76838 , H05K3/24
摘要： A ground pattern film 12 for interconnections is formed on a glass substrate 11, and a plating film 13 is formed by selective plating on the ground pattern film 12. A taper angle &agr; which both sides of the plating film 13 form with the surface of the glass substrate 11 is made in the range of 0

4. 发明授权

US06603206B2 Slot via filled dual damascene interconnect structure without middle etch stop layer 有权
标题翻译：通过填充的双镶嵌互连结构的槽，没有中间蚀刻停止层
公开(公告)号：US06603206B2
公开(公告)日：2003-08-05
申请号：US10105509
申请日：2002-03-26
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L23522
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031 , Y10S977/827
摘要： An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中底部抗反射涂层/蚀刻停止层沉积在导电层上。无机低k介电材料沉积在BARC /蚀刻停止层上以形成第一介电层。蚀刻第一介电层以在第一介电层中形成槽通孔。有机低k电介质材料通过第一电介质层和第一介电层上方沉积在槽内，以在槽通孔和第一介电层上形成第二电介质层。再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽沿与槽通孔的长度垂直的方向延伸。沟槽的整个宽度直接在通孔上方。重新打开的通孔和沟槽填充有导电材料。

5. 发明授权

US06414394B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06414394B1
公开(公告)日：2002-07-02
申请号：US09531011
申请日：2000-03-20
申请人： Sachiyo Ito , Masahiko Hasunuma
发明人： Sachiyo Ito , Masahiko Hasunuma
IPC分类号： H01L23522
CPC分类号： H01L23/5329 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device is structured to include a wiring made of Al, a first insulation film made of silicon oxide including an organic content formed in contact with an upper surface of the wiring, and a second insulation film formed in contact with an upper surface of the first insulation film and made of an F-added SiO2 film having a higher Young's modulus than that of the first insulation film. The wiring has a film thickness dM of 400 nm, the first insulation film has a film thickness ds of 400 nm, and the second insulation film has a film thickness dh of 10 nm.
摘要翻译：半导体器件被构造成包括由Al制成的布线，由氧化硅制成的第一绝缘膜，所述氧化硅包括与布线的上表面接触形成的有机物质，以及第二绝缘膜，其形成为与所述布线的上表面接触第一绝缘膜，并且由具有比第一绝缘膜的杨氏模量高的F加入的SiO 2膜制成。布线的膜厚dM为400nm，第一绝缘膜的膜厚ds为400nm，第二绝缘膜的膜厚dh为10nm。

6. 发明授权

US06828679B2 Solid image pickup device 失效
标题翻译：固体图像拾取装置
公开(公告)号：US06828679B2
公开(公告)日：2004-12-07
申请号：US10420706
申请日：2003-04-23
申请人： Teiji Azumi
发明人： Teiji Azumi
IPC分类号： H01L23522
CPC分类号： H01L27/14683 , H01L27/14812 , H01L27/14831
摘要： The invention is to provide a solid image pickup device having high electric pressure proof between charge transfer electrodes of mono-layered structure, and enabling to drive at high speed with low consumption electric power. In this invention, a silicone base is formed on a surface thereof with an insulating film, on a surface of which inter-electrode insulating films of an oxidized silicone film and charge transfer electrodes are provided. The charge transfer electrode includes an adhesion film so formed as to cover a side wall of the inter-electrode insulating film and a gate insulating film as well as a conductive film containing metals in an area surrounded with the adhesion film. The adhesion film is formed with, e.g., polycrystalline silicone of highly dense dope, while the conductive film is formed with, e.g., a tungsten layer. The charge transfer electrode is formed on the upper face with the oxidized silicone film.
摘要翻译：本发明提供一种在单层结构的电荷传输电极之间具有高电压力的固体摄像装置，并能够以低功耗电力高速驱动。在本发明中，在其表面上形成有绝缘膜的硅氧烷基底，其表面上设有氧化硅酮薄膜和电荷转移电极的电极间绝缘膜。电荷转移电极包括形成为覆盖电极间绝缘膜的侧壁和栅极绝缘膜的粘合膜以及在由粘合膜包围的区域中含有金属的导电膜。粘合膜由高密度掺杂的多晶硅形成，而导电膜由例如钨层形成。电荷转移电极在氧化的硅氧烷膜的上表面上形成。

7. 发明授权

US06617681B1 Interposer and method of making same 有权
公开(公告)号：US06617681B1
公开(公告)日：2003-09-09
申请号：US09340530
申请日：1999-06-28
申请人： Mark T. Bohr
发明人： Mark T. Bohr
IPC分类号： H01L23522
CPC分类号： H01L23/147 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/16 , H01L2224/16 , H01L2224/16225 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49165
摘要： A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

8. 发明授权

US06342733B1 Reduced electromigration and stressed induced migration of Cu wires by surface coating 有权
公开(公告)号：US06342733B1
公开(公告)日：2002-01-29
申请号：US09361573
申请日：1999-07-27
申请人： Chao-Kun Hu , Robert Rosenberg , Judith Marie Rubino , Carlos Juan Sambucetti , Anthony Kendall Stamper
发明人： Chao-Kun Hu , Robert Rosenberg , Judith Marie Rubino , Carlos Juan Sambucetti , Anthony Kendall Stamper
IPC分类号： H01L23522
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76864 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

9. 发明授权

US06580171B2 Semiconductor wiring device 有权
公开(公告)号：US06580171B2
公开(公告)日：2003-06-17
申请号：US10085067
申请日：2002-03-01
申请人： Sachiyo Ito , Masahiko Hasunuma
发明人： Sachiyo Ito , Masahiko Hasunuma
IPC分类号： H01L23522
CPC分类号： H01L23/5329 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device is structured to include a wiring made of Al, a first insulation film made of silicon oxide including an organic content formed in contact with an upper surface of the wiring, and a second insulation film formed in contact with an upper surface of the first insulation film and made of an F-added SiO2 film having a higher Young's modulus than that of the first insulation film. The wiring has a film thickness dM of 400 nm, the first insulation film has a film thickness ds of 400 nm, and the second insulation film has a film thickness dh of 10 nm.

10. 发明授权

US06492732B2 Interconnect structure with air gap compatible with unlanded vias 有权
标题翻译：互连结构与空隙兼容，与非接地通孔
公开(公告)号：US06492732B2
公开(公告)日：2002-12-10
申请号：US09849666
申请日：2001-05-04
申请人： Ellis Lee , Shih-Wei Sun
发明人： Ellis Lee , Shih-Wei Sun
IPC分类号： H01L23522
CPC分类号： H01L21/7682 , H01L21/76802
摘要： An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure. The opening may also expose a top portion of a sidewall of the conductive structure if a misalignment occurs, but the opening does not expose the air gap due to protection from the predetermined distance of the capping layer within the air gap. A next level of conductive structure can be formed to fill the opening. A liner layer can be also formed on a sidewall of the substructure interfacing the air gap, so as to protect the conductive structure.
摘要翻译：互连结构具有其上已经形成有器件的衬底。电介质层覆盖在衬底上。在电介质层上形成具有至少两个由气隙分隔的子结构的导电结构。覆盖层覆盖导电结构和气隙。在气隙上方的一部分上的覆盖层也填充到气隙中预定的距离。气隙也可以延伸到电介质层中以具有更大的高度。在覆盖层上形成蚀刻停止层。在蚀刻停止层上形成金属间介电层。将金属间介电层，蚀刻停止层和覆盖层图案化以形成露出导电结构的顶表面的开口。如果发生不对准，则开口也可能暴露出导电结构的侧壁的顶部部分，但是由于防止气隙内的封盖层的预定距离的保护，开口不暴露气隙。可以形成下一级的导电结构以填充开口。衬垫层也可以形成在与气隙接合的子结构的侧壁上，以便保护导电结构。

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