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1. 发明授权

US06454916B1 Selective electroplating with direct contact chemical polishing 失效
标题翻译：选择性电镀与直接接触化学抛光
公开(公告)号：US06454916B1
公开(公告)日：2002-09-24
申请号：US09477810
申请日：2000-01-05
申请人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
发明人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
IPC分类号： C25D1700
CPC分类号： C25D5/22 , B23H5/08 , C25D7/12 , C25D17/001
摘要： A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.
摘要翻译：沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。电镀材料填充图案化到半导体晶片的衬底中的凹槽，但是由于扩散器的接触和旋转，防止了在半导体晶片的顶表面上形成很大程度。由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上，所以化学机械抛光（CMP）平面化被显着地减少或完全消除。

2. 发明授权

US06319834B1 Method and apparatus for improved planarity metallization by electroplating and CMP 有权
标题翻译：通过电镀和CMP改善平面度金属化的方法和装置
公开(公告)号：US06319834B1
公开(公告)日：2001-11-20
申请号：US09639812
申请日：2000-08-17
申请人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
发明人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
IPC分类号： H01L2144
CPC分类号： H01L21/3212 , H01L21/2885 , H01L21/7684 , H01L21/76877 , H01L21/76879
摘要： A pattern of in-laid conductors is formed by a method utilizing electroplating and chemical-mechanical polishing (CMP). Embodiments include a first step of selectively filling recesses formed in the surface of a substrate with a metal by localized electroplating at a reduced thickness, planar-surfaced overburden or blanket layer thereon, and planarizing the surface by CMP utilizing a relatively soft CMP pad. Embodiments also include an apparatus comprising a porous pad applicator for selectively electroplating recesses formed in the surface of a workpiece.
摘要翻译：通过使用电镀和化学机械抛光（CMP）的方法形成嵌入导体的图案。实施例包括第一步骤，通过局部电镀在其上以薄的局部电镀，平面表面覆盖层或覆盖层选择性地填充形成在衬底的表面中的凹陷，并且通过使用相对较软的CMP衬垫的CMP来平坦化表面。实施例还包括一种包括用于选择性地电镀在工件表面中形成的凹槽的多孔垫施加器的装置。

3. 发明授权

US07157795B1 Composite tantalum nitride/tantalum copper capping layer 有权
标题翻译：复合氮化钽/钽铜覆盖层
公开(公告)号：US07157795B1
公开(公告)日：2007-01-02
申请号：US10934511
申请日：2004-09-07
申请人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
发明人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L21/76849 , Y10S438/927
摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.
摘要翻译：通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

4. 发明授权

US06169034A Chemically removable Cu CMP slurry abrasive 有权
标题翻译：化学去除Cu CMP浆料研磨剂
公开(公告)号：US06169034A
公开(公告)日：2001-01-02
申请号：US09199352
申请日：1998-11-25
申请人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
发明人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
IPC分类号： H01L21461
CPC分类号： H01L21/3212 , C09G1/02 , C09K3/1463
摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of soft mineral particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing magnesium oxide particles and removing any residual magnesium oxide particles after CMP with an organic acid, such as citric acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, phosphoric, boric or fluoboric acid.
摘要翻译：在CMP期间对Cu金属化的磨损降低，并且通过使用含有在稀酸中具有高溶解度的软矿物颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。实施方案包括用含有氧化镁颗粒的浆料进行CMP Cu金属化，并在CMP之后用有机酸如柠檬酸或乙酸或稀无机酸如盐酸，磷酸，硼酸或氟硼酸除去残留的氧化镁颗粒。

5. 发明授权

US6140239A Chemically removable Cu CMP slurry abrasive 有权
标题翻译：化学去除Cu CMP浆料研磨剂
公开(公告)号：US6140239A
公开(公告)日：2000-10-31
申请号：US199266
申请日：1998-11-25
申请人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
发明人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
IPC分类号： H01L21/02 , H01L21/306 , H01L21/321 , H01L21/304
CPC分类号： H01L21/02074 , H01L21/3212
摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of iron oxide particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing iron oxide particles and removing residual iron oxide particles after CMP with an organic acid, such as oxalic acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, boric or fluoroboric acid.
摘要翻译：在CMP期间对Cu金属化的磨损减少，并且通过使用含有在稀酸中具有高溶解度的氧化铁颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。实施方案包括用含有氧化铁颗粒的浆料和CMP之后用有机酸如草酸或乙酸除去残留的氧化铁颗粒，或稀释的无机酸如盐酸，硼酸或氟硼酸的CMP Cu金属化。

6. 发明授权

US06756306B2 Low temperature dielectric deposition to improve copper electromigration performance 有权
标题翻译：低温介电沉积提高铜电迁移性能
公开(公告)号：US06756306B2
公开(公告)日：2004-06-29
申请号：US10334387
申请日：2002-12-30
申请人： Steven C. Avanzino , Darrell M. Erb
发明人： Steven C. Avanzino , Darrell M. Erb
IPC分类号： H01L2144
CPC分类号： H01L21/02118 , H01L21/02167 , H01L21/02271 , H01L21/312 , H01L21/314 , H01L21/76801 , H01L21/76829 , H01L21/76834
摘要： The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.
摘要翻译：通过用于在金属化图案上沉积钝化层的化学气相沉积工艺来增强镶嵌在介电材料层的表面中的平坦化金属化特征（例如铜）的可靠性和电迁移寿命，其包括保持在上部处于或低于第一温度的金属化特征的表面是预先沉积在其上的抑制膜。抑制膜基本上抑制在第一温度以下的金属化特征的表面上形成氧化物层。钝化层沉积在高于第一温度的第二温度下发生，使得去除抑制膜和钝化层的形成之间的时间间隔足够短，从而基本上抑制金属特征表面上的氧化物的形成。

7. 发明授权

US06500754B1 Anneal hillock suppression method in integrated circuit interconnects 有权
标题翻译：集成电路互连中的退火小丘抑制方法
公开(公告)号：US06500754B1
公开(公告)日：2002-12-31
申请号：US09999661
申请日：2001-10-31
申请人： Darrell M. Erb , Steven C. Avanzino , Alline F. Myers
发明人： Darrell M. Erb , Steven C. Avanzino , Alline F. Myers
IPC分类号： H01L214763
CPC分类号： H01L21/76883
摘要： An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400° C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.
摘要翻译：因此，提供了具有半导体器件的半导体衬底的集成电路和制造方法。在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。在导体芯和阻挡层平坦化之前，在400℃及以上的高温下进行半导体衬底的退火以刺激晶粒生长。在平坦化之后，随后的钝化层或覆盖层的高温沉积将不会导致晶粒生长并且抑制小丘。

8. 发明授权

US07232765B1 Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures 有权
标题翻译：在铜上利用含Ta的盖以促进铜通孔和记忆元件结构的同时形成
公开(公告)号：US07232765B1
公开(公告)日：2007-06-19
申请号：US10988239
申请日：2004-11-12
申请人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
发明人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76849 , H01L21/7685 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L51/0021
摘要： Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non-memory element forming copper plugs (non-memE copper plugs), forming a tantalum-containing cap over an upper surface of non-memE copper plugs, and depositing memory element films. The tantalum-containing cap prevents the formation of the memory element films in the non-memE copper plugs. The subject invention advantageously facilitates cost-effective manufacturing of semiconductor devices.
摘要翻译：公开了促进铜通孔和记忆元件结构的同时形成的方法。所述方法包括在金属线上形成通孔并形成铜塞，其中铜塞包括记忆元件膜形成铜塞（memE铜塞）和形成铜塞（非memE铜塞）的非存储元件，形成含钽覆盖非memE铜插头的上表面，并沉积存储元件膜。含钽盖防止在非memE铜插头中形成记忆元件膜。本发明有利地有助于半导体器件的成本有效的制造。

9. 发明授权

US06528409B1 Interconnect structure formed in porous dielectric material with minimized degradation and electromigration 有权
标题翻译：在多孔介电材料中形成的互连结构具有最小化的降解和电迁移
公开(公告)号：US06528409B1
公开(公告)日：2003-03-04
申请号：US10134883
申请日：2002-04-29
申请人： Sergey Lopatin , Fei Wang , Diana Schonauer , Steven C. Avanzino
发明人： Sergey Lopatin , Fei Wang , Diana Schonauer , Steven C. Avanzino
IPC分类号： H01L214763
CPC分类号： H01L21/76828 , H01L21/288 , H01L21/76805 , H01L21/76814 , H01L21/7682 , H01L21/76829 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76849 , H01L21/76862 , H01L21/76865 , H01L21/76867 , H01L21/76874 , H01L2221/1047 , H01L2221/1089
摘要： For fabricating an interconnect structure within an interconnect opening formed within a porous dielectric material, the interconnect opening is initially formed within a low-K precursor material that is not completely cured. The interconnect opening is then filled with a conductive fill material being contained within the interconnect opening and with a top surface of the conductive fill material within the interconnect opening being exposed. A capping material is formed on the top surface of the conductive fill material, and the capping material is an amorphous alloy or is a microcrystalline alloy having stuffed grain boundaries. A thermal curing process is then performed for curing the low-K precursor material to become a porous low-K dielectric material. The capping material on the top surface of the conductive fill material is impervious to at least one of oxygen, carbon, hydrogen, chlorine, and porogen fragments that are generated as out-gassing volatile by-products from the low-K precursor material during the thermal curing process to preserve the integrity of the interconnect structure. In another aspect for fabricating an interconnect structure, an interconnect opening is formed within a porous dielectric material with opened pores at sidewalls of the interconnect opening. A diffusion barrier material is formed at a bottom wall of the interconnect opening. The diffusion barrier material is then sputtered away from the bottom wall of the interconnect opening and onto the sidewalls of the interconnect opening to substantially fill the opened pores at the sidewalls with the diffusion barrier material. The interconnect opening is then filled with a conductive fill material after the opened pores at the sidewalls of the interconnect opening are filled with the diffusion barrier material.
摘要翻译：为了在形成在多孔电介质材料内的互连开口内制造互连结构，互连开口最初形成在未完全固化的低K前体材料内。然后用互连开口内容纳的导电填充材料填充互连开口，并且暴露互连开口内的导电填充材料的顶表面。在导电填充材料的顶表面上形成封盖材料，封盖材料是非晶合金，或是具有填充晶界的微晶合金。然后进行热固化过程，以固化低K前体材料，成为多孔低K电介质材料。在导电填充材料的顶表面上的封盖材料对于氧，碳，氢，氯和致孔剂碎片中的至少一种是不渗透的，所述氧，碳，氢，氯和致孔剂碎片作为在低K前体材料期间产生的挥发性挥发性副产物而产生热固化工艺来保持互连结构的完整性。在用于制造互连结构的另一方面中，互连开口形成在具有在互连开口的侧壁处的开孔的多孔电介质材料内。扩散阻挡材料形成在互连开口的底壁处。然后将扩散阻挡材料从互连开口的底壁溅射到互连开口的侧壁上，以基本上用扩散阻挡材料填充侧壁处的开孔。然后在互连开口的侧壁处的开放孔填充有扩散阻挡材料之后，用导电填充材料填充互连开口。

10. 发明授权

US07776682B1 Ordered porosity to direct memory element formation 有权
标题翻译：有序孔隙直接记忆元素形成
公开(公告)号：US07776682B1
公开(公告)日：2010-08-17
申请号：US11110165
申请日：2005-04-20
申请人： Alexander Nickel , Suzette K. Pangrle , Steven C. Avanzino , Jeffrey Shields , Fei Wang , Minh Tran , Juri H. Krieger , Igor Sokolik
发明人： Alexander Nickel , Suzette K. Pangrle , Steven C. Avanzino , Jeffrey Shields , Fei Wang , Minh Tran , Juri H. Krieger , Igor Sokolik
IPC分类号： H01L21/8242
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/085 , H01L45/1246 , H01L45/1266 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/146 , H01L45/149 , H01L45/1616
摘要： Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.
摘要翻译：公开了用于改善记忆单元中电性能的细胞间细胞重复性的方法和系统。所述方法包括在无源层上形成具有有序孔隙率的非导电材料。有序孔隙度可以促进导电通道的形成，电荷载体可以穿过导电通道迁移穿过另外的非导电层以便于改变存储器单元的状态。可以可选地在非导电层上形成阻挡层，并且可以以基本上垂直于导电沟道的方式定向排序的孔隙，使得穿过非导电层迁移的电荷不能渗透到阻挡层。该方法提供了具有成本效益和电可靠性的存储单元的微电子器件的制造。

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