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1. 发明授权

US06956260B2 Integrated semiconductor memory with wordlines conductively connected to one another in pairs 失效
标题翻译：集成半导体存储器，其字线彼此成对地导电连接
公开(公告)号：US06956260B2
公开(公告)日：2005-10-18
申请号：US10463019
申请日：2003-06-17
申请人： Dirk Manger , Till Schlösser , Martin Popp , Michael Sesterhenn
发明人： Dirk Manger , Till Schlösser , Martin Popp , Michael Sesterhenn
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10891
摘要： In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.
摘要翻译：在半导体存储器中，特别是DRAM，其存储单元在由衬底材料形成的垂直焊盘处具有垂直晶体管，栅电极形成为围绕焊盘运行的间隔件。相邻存储单元的栅电极通常必须追溯地连接以形成字线。已知用相邻的焊盘之间的空间填充氧化物，结果是间隔件直接形成为字线，而仅覆盖焊盘的两个侧壁。并联连接的两个晶体管形成在这些侧壁而不是单个晶体管，因为栅电极不会绕着焊盘运行。本发明提出一种半导体存储器的制造方法，其中，由字线覆盖焊盘的四个侧壁，同时通过字线将相邻存储单元的焊盘相互连接。

2. 发明授权

US07368752B2 DRAM memory cell 失效
标题翻译： DRAM存储单元
公开(公告)号：US07368752B2
公开(公告)日：2008-05-06
申请号：US10839800
申请日：2004-05-06
申请人： Richard J. Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rösner , Till Schlösser , Michael Specht
发明人： Richard J. Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rösner , Till Schlösser , Michael Specht
IPC分类号： H01L27/108 , H01L29/12 , H01L31/112
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.
摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器，所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

3. 发明授权

US06750098B2 Integrated semiconductor memory and fabrication method 有权
标题翻译：集成半导体存储器和制造方法
公开(公告)号：US06750098B2
公开(公告)日：2004-06-15
申请号：US10619970
申请日：2003-07-15
申请人： Till Schlösser , Dirk Manger
发明人： Till Schlösser , Dirk Manger
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10888 , H01L27/10891 , H01L29/66666
摘要： In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.
摘要翻译：在具有围绕栅极结构的半导体存储器中，在半导体衬底的表面上形成由衬底材料制成的腹板，即垂直矩形柱，并且在下部区域中由栅电极包围。通常，字线不可能与幅材的下部区域中的栅极电极接触，而不会同时在幅材或短路位线从其侧壁电位影响衬底区域的较高水平，除非使用需要额外光刻步骤的复杂方法。借助于具有比外围栅极电极更薄的层厚度的绝缘层来执行外围栅电极的自对准，选择性接触连接的方法。

4. 发明授权

US06861688B2 Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with a line configuration and method for fabricating a line configuration 有权
标题翻译：用于连接至少一个存储单元的位线的线路配置，具有线路配置的半导体部件和用于制造线路配置的方法
公开(公告)号：US06861688B2
公开(公告)日：2005-03-01
申请号：US10288387
申请日：2002-11-05
申请人： Dirk Manger , Till Schlösser
发明人： Dirk Manger , Till Schlösser
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/10885
摘要： A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory cell. A first bit line in a first bit line level is disposed below a second bit line in a second bit line level and the second bit line penetrates through the first bit line at at least one location of the first bit line for the purpose of producing a contact with the at least one memory cell at penetration locations. It is thus possible to provide space-saving structures, in particular sub-8F2 structures.
摘要翻译：用于接触连接至少一个存储器单元，特别是DRAM存储单元的位线配置具有位于存储单元的平面之上的位线。第一位线电平中的第一位线设置在第二位线电平中的第二位线下方，并且第二位线在第一位线的至少一个位置处穿过第一位线，以产生第在穿透位置处与至少一个存储单元接触。因此，可以提供节省空间的结构，特别是8F 2结构。

5. 发明授权

US07829892B2 Integrated circuit including a gate electrode 有权
标题翻译：集成电路包括栅电极
公开(公告)号：US07829892B2
公开(公告)日：2010-11-09
申请号：US11926653
申请日：2007-10-29
申请人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
发明人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
IPC分类号： H01L29/12
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅极电极将沟道层包围至少两个相对的侧面。

6. 发明授权

US07825031B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07825031B2
公开(公告)日：2010-11-02
申请号：US11855809
申请日：2007-09-14
申请人： Dirk Manger , Rolf Weis , Christoph Noelscher
发明人： Dirk Manger , Rolf Weis , Christoph Noelscher
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76816
摘要： The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.
摘要翻译：本发明涉及一种制造集成电路的方法，包括提供至少一层的步骤; 执行第一注入步骤，其中在第一入射方向上将颗粒注入所述层中; 执行第二注入步骤，其中在与所述第一入射方向不同的第二入射方向上将颗粒注入所述层中; 执行去除步骤，其中根据由第一和第二植入步骤产生的局部植入剂量部分去除该层。

7. 发明申请

US20090033362A1 Method for Forming a Structure on a Substrate and Device 失效
标题翻译：在基板和设备上形成结构的方法
公开(公告)号：US20090033362A1
公开(公告)日：2009-02-05
申请号：US11831504
申请日：2007-07-31
申请人： Dirk Manger , Stephan Wege , Rolf Weis , Christoph Noelscher
发明人： Dirk Manger , Stephan Wege , Rolf Weis , Christoph Noelscher
IPC分类号： H01R43/00 , H01L21/02 , H01L21/31
CPC分类号： H01L21/266 , H01L21/0332 , H01L21/0337 , H01L21/31111 , H01L21/31144 , H01L21/32134 , H01L21/32135 , H01L21/32137 , H01L21/32139
摘要： In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.
摘要翻译：一方面，公开了一种在衬底上形成结构的方法。例如，该方法包括形成第一掩模层和第二掩模层，改变第一和第二掩模层的区域中的材料特性，以及基于改质区域形成结构。

8. 发明申请

US20050088895A1 DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
标题翻译：具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法
公开(公告)号：US20050088895A1
公开(公告)日：2005-04-28
申请号：US10897687
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
IPC分类号： G11C11/34
CPC分类号： H01L27/10841 , H01L27/10867
摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.
摘要翻译：在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏极电容的减小以及栅电极和漏极电极之间的漏电流较低的源极/漏极区域。施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构单元晶体管。

9. 发明授权

US07662721B2 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US07662721B2
公开(公告)日：2010-02-16
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L21/461
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层堆叠包括设置在待图案化层的顶部上的碳层，选自设置在碳层顶部上的SiO 2和SiON中的第一层材料和硅层设置在第一层的顶部。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

10. 发明申请

US20080054324A1 INTEGRATED CIRCUIT INCLUDING A GATE ELECTRODE 有权
标题翻译：集成电路，包括门电极
公开(公告)号：US20080054324A1
公开(公告)日：2008-03-06
申请号：US11926653
申请日：2007-10-29
申请人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
发明人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
IPC分类号： H01L29/94
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅电极在至少两个相对的两侧包围沟道层。

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