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1. 发明申请

US20050088895A1 DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
标题翻译：具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法
公开(公告)号：US20050088895A1
公开(公告)日：2005-04-28
申请号：US10897687
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller , Joachim Nuetzel , Klaus Muemmler
IPC分类号： G11C11/34
CPC分类号： H01L27/10841 , H01L27/10867
摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.
摘要翻译：在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏极电容的减小以及栅电极和漏极电极之间的漏电流较低的源极/漏极区域。施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构单元晶体管。

2. 发明申请

US20050083724A1 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
标题翻译：具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法
公开(公告)号：US20050083724A1
公开(公告)日：2005-04-21
申请号：US10898706
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
IPC分类号： G11C11/34 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.
摘要翻译：每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏极电容的减小以及栅电极和漏电极之间的漏电流较低的源极/漏极区域。用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。单元晶体管的上源/漏区通过接触孔注入而形成。

3. 发明授权

US07141845B2 DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
标题翻译：具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法
公开(公告)号：US07141845B2
公开(公告)日：2006-11-28
申请号：US10898706
申请日：2004-07-23
申请人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
发明人： Dirk Manger , Till Schloesser , Rolf Weis , Bernd Goebel , Wolfgang Mueller
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.
摘要翻译：每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏极电容的减小以及栅电极和漏电极之间的漏电流较低的源极/漏极区域。用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。单元晶体管的上源/漏区通过接触孔注入而形成。

4. 发明授权

US07442609B2 Method of manufacturing a transistor and a method of forming a memory device with isolation trenches 失效
标题翻译：制造晶体管的方法和形成具有隔离沟槽的存储器件的方法
公开(公告)号：US07442609B2
公开(公告)日：2008-10-28
申请号：US11222613
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Richard Johannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Richard Johannes Luyken
IPC分类号： H01L21/336
CPC分类号： H01L27/10823 , G11C11/404 , H01L21/76897 , H01L27/0207 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.
摘要翻译：一种制造晶体管的方法。在一个实施例中，该方法包括通过在衬底中限定栅极沟槽来形成栅电极。在与沟槽相邻的位置上的每个沟槽中限定了板状部分，使得两个板状部分将与沟槽连接，并且沟槽设置在两个板状部分之间。在一个实施例中，通过蚀刻工艺限定两个板状部分，该蚀刻工艺相对于半导体衬底材料选择性地蚀刻隔离沟槽的隔离材料。栅极绝缘材料设置在有源区域和沟槽之间的界面以及有源区域和板状部分之间的界面处，并且沉积栅电极材料以填充沟槽和两个板状部分。

5. 发明授权

US07763513B2 Integrated circuit device and method of manufacture 失效
标题翻译：集成电路器件及其制造方法
公开(公告)号：US07763513B2
公开(公告)日：2010-07-27
申请号：US11222540
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28114 , H01L27/10876 , H01L27/10894 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.
摘要翻译：公开了制造晶体管的方法。该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间口袋栅极绝缘材料设置在有源区域和凹槽之间的界面处以及在有源区域和凹穴之间的界面处。沉积栅电极材料以填充凹槽和两个凹穴。

6. 发明申请

US20070057301A1 Method of manufacturing a transistor, a method of manufacturing a memory device and transistor 失效
标题翻译：制造晶体管的方法，制造存储器件和晶体管的方法
公开(公告)号：US20070057301A1
公开(公告)日：2007-03-15
申请号：US11222540
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
IPC分类号： H01L29/94
CPC分类号： H01L29/66621 , H01L21/28114 , H01L27/10876 , H01L27/10894 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.
摘要翻译：公开了制造晶体管的方法。该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间口袋栅极绝缘材料设置在有源区域和凹槽之间的界面处以及有源区域和凹穴之间的界面处。沉积栅电极材料以填充凹槽和两个凹穴。

7. 发明申请

US20060110884A1 Method of manufacturing a transistor and a method of forming a memory device 失效
标题翻译：制造晶体管的方法和形成存储器件的方法
公开(公告)号：US20060110884A1
公开(公告)日：2006-05-25
申请号：US11222613
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
IPC分类号： H01L21/336
CPC分类号： H01L27/10823 , G11C11/404 , H01L21/76897 , H01L27/0207 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the isolation trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between the two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.
摘要翻译：一种制造晶体管的方法。在一个实施例中，该方法包括通过在衬底中限定栅极沟槽来形成栅电极。在每个隔离沟槽中的与槽相邻的位置处限定板状部分，使得两个板状部分将与沟槽连接，并且沟槽设置在两个板状部分之间。在一个实施例中，通过蚀刻工艺限定两个板状部分，该蚀刻工艺相对于半导体衬底材料选择性地蚀刻隔离沟槽的隔离材料。栅极绝缘材料设置在有源区域和沟槽之间的界面处，并且在有源区域和板状部分之间的界面处设置，并且沉积栅电极材料以填充沟槽和两个板状部分。

8. 发明授权

US07687343B2 Storage capacitor, a memory device and a method of manufacturing the same 有权
标题翻译：存储电容器，存储器件及其制造方法
公开(公告)号：US07687343B2
公开(公告)日：2010-03-30
申请号：US11633090
申请日：2006-12-04
申请人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
发明人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.
摘要翻译：存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。绝缘层的下侧设置在第一电容器部分的上侧的高度处。

9. 发明申请

US20080128773A1 Storage capacitor, a memory device and a method of manufacturing the same 有权
标题翻译：存储电容器，存储器件及其制造方法
公开(公告)号：US20080128773A1
公开(公告)日：2008-06-05
申请号：US11633090
申请日：2006-12-04
申请人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
发明人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
IPC分类号： H01L27/108
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.
摘要翻译：存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。绝缘层的下侧设置在第一电容器部分的上侧的高度处。

10. 发明授权

US07727837B2 Method of producing an integrated circuit having a capacitor with a supporting layer 失效
标题翻译：一种具有带支撑层的电容器的集成电路的制造方法
公开(公告)号：US07727837B2
公开(公告)日：2010-06-01
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/302 , H01L21/461
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

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