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1. 发明申请

US20060022248A1 Electronic data memory device for a high read current 审中-公开
标题翻译：用于高读取电流的电子数据存储器件
公开(公告)号：US20060022248A1
公开(公告)日：2006-02-02
申请号：US11167386
申请日：2005-06-27
申请人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
发明人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10873 , H01L29/7851
摘要： Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).
摘要翻译：用于高读取电流的电子数据存储器件本发明提供一种布置在衬底（401）上并具有至少一个存储单元（100）的存储器件。存储单元包括用于存储电荷的存储电容器（200）晶体管（300），用于选择存储单元（100）。选择晶体管包括第一导电电极（301），第二导电电极（302）和控制电极（303），控制电极（303）由栅极单元（400）提供，栅极单元（400）具有从基板（401），其被栅极氧化物层（406）和栅极电极层（403）包围，使得第一和第二栅极元件（408a，408b）设置在第一和第二栅极元件（408a，408b）的相对侧向区域所述翅片（405），第三栅极元件（408c）设置在所述鳍状物（405）的与所述基板（401）的表面平行的区域。

2. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

3. 发明申请

US20050201187A1 Integrated read-only memory, method for operating said read-only memory and corresponding production method 有权
标题翻译：集成只读存储器，用于操作所述只读存储器的方法和相应的制造方法
公开(公告)号：US20050201187A1
公开(公告)日：2005-09-15
申请号：US10505320
申请日：2003-02-17
申请人： Franz Hofmann , Richard Luyken , Till Schlosser
发明人： Franz Hofmann , Richard Luyken , Till Schlosser
IPC分类号： H01L27/10 , G11C8/02 , G11C16/02 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L27/24 , H01L27/28
CPC分类号： H01L27/28 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/147
摘要： An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
摘要翻译：具有选择晶体管的集成只读存储器，每个具有漏极连接和用于馈送诸如电压或电流的电信号的电极连接。在漏极连接和电极之间设置一层，其电阻可以在配置电压或电流的作用下改变。该层可以应用在后端进程中。

4. 发明申请

US20050199942A1 Semiconductor memory with vertical memory transistors and method for fabricating it 有权
标题翻译：具有垂直存储晶体管的半导体存储器及其制造方法
公开(公告)号：US20050199942A1
公开(公告)日：2005-09-15
申请号：US11073205
申请日：2005-03-05
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.
摘要翻译：本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层，以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

5. 发明申请

US20050100938A1 Vertical impedance sensor arrangement and method for producing a vertical impedance sensor arrangement 审中-公开
标题翻译：垂直阻抗传感器布置和垂直阻抗传感器布置方法
公开(公告)号：US20050100938A1
公开(公告)日：2005-05-12
申请号：US10939319
申请日：2004-09-09
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
IPC分类号： C12Q1/68 , G01N33/543
CPC分类号： G01N33/54386 , G01N27/3276
摘要： Vertical impedance sensor arrangement including a substrate, a first electrically conductive structure having a first uncovered surface and being arranged in and/or on the substrate, a spacer arranged above the substrate and/or at least partially on the first electrically conductive structure, a second electrically conductive structure having a second uncovered surface and being arranged on the spacer, and capture molecules, which are immobilized on the first and on the second uncovered surface, are set up such that particles to be detected hybridize with the capture molecules. The spacer is formed separately from the substrate, and the thickness of the spacer is defined by means of a deposition method.
摘要翻译：垂直阻抗传感器布置包括基底，具有第一未覆盖表面并布置在基底中和/或基底上的第一导电结构，布置在基底上和/或至少部分地在第一导电结构上的间隔物，第二具有第二未覆盖表面并布置在间隔物上的导电结构，并且被固定在第一和第二未覆盖表面上的捕获分子被设置成使得待检测的颗粒与捕获分子杂交。间隔物与衬底分开形成，并且通过沉积方法限定间隔物的厚度。

6. 发明申请

US20070096196A1 Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement 有权
标题翻译：翅片场效应晶体管布置及其制造方法
公开(公告)号：US20070096196A1
公开(公告)日：2007-05-03
申请号：US11588868
申请日：2006-10-27
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken
IPC分类号： H01L29/788 , H01L21/84 , H01L21/8238 , H01L27/12 , H01L21/00 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785 , H01L29/78636
摘要： A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.
摘要翻译：鳍状场效应晶体管布置包括衬底和衬底上和/或衬底中的第一鳍状场效应晶体管。第一鳍状场效应晶体管包括鳍状物，其中在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域，并且在其上形成栅极区域。第二鳍状场效应晶体管设置在衬底上和/或衬底中，包括在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域的鳍片，并且在其上形成栅极区域。第二鳍状场效应晶体管沿第一鳍状场效应晶体管横向布置，其中第一鳍状场效应晶体管的鳍的高度大于第二鳍状场效应晶体管的鳍的高度。

7. 发明申请

US20060022275A1 Planar dual-gate transistor and method for fabricating a planar dual-gate transistor 审中-公开
标题翻译：平面双栅晶体管和制造平面双栅晶体管的方法
公开(公告)号：US20060022275A1
公开(公告)日：2006-02-02
申请号：US11177235
申请日：2005-07-07
申请人： Gurkan llicali , Richard Luyken , Wolfgang Roesner
发明人： Gurkan llicali , Richard Luyken , Wolfgang Roesner
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/66628 , H01L29/78618 , H01L29/78648
摘要： A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.
摘要翻译：一种用于制造双栅极晶体管的方法，包括在SOI衬底上限定有源区，在SOI衬底上形成第一栅极区，在有源区中形成由硅 - 锗制成的源极/漏极区，从而形成来自硅层，形成在SOI衬底上方具有平坦表面的层，源极/漏极区和第一栅极区，将第二晶片接合到平坦表面，以及形成与第一栅极相对的第二栅极区地区。

8. 发明申请

US20050199912A1 Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F2 cells 失效
标题翻译：具有垂直存储晶体管的半导体存储器，其具有1-2F2个单元阵列
公开(公告)号：US20050199912A1
公开(公告)日：2005-09-15
申请号：US11073214
申请日：2005-03-05
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/73 , H01L29/76 , H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2 per bit can thus be achieved.
摘要翻译：本发明涉及一种具有多个存储单元的半导体存储器，每个存储器单元具有N（例如四个）垂直存储晶体管，具有捕获层。在相对于单元阵列的行和列倾斜地延伸的较高半导体区域中形成更高的接触区域，栅电极通常被引导到较高半导体区域的台阶侧区域。因此可以实现每位1-2F 2的存储密度。

9. 发明授权

US07635867B2 Nanotube array and method for producing a nanotube array 失效
标题翻译：纳米管阵列及其制造方法
公开(公告)号：US07635867B2
公开(公告)日：2009-12-22
申请号：US10476663
申请日：2002-05-16
申请人： Andrew Graham , Franz Hofmann , Johannes Kretz , Franz Kreupl , Richard Luyken , Wolfgang Rösner
发明人： Andrew Graham , Franz Hofmann , Johannes Kretz , Franz Kreupl , Richard Luyken , Wolfgang Rösner
IPC分类号： H01L31/0312
CPC分类号： H01L51/0048 , B82Y10/00 , C01B32/05 , G01N27/127 , G11C13/025 , H01L51/0595
摘要： A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer. This electrically insulating layer preferably has a topography which is such that the at least one nanotube rests on the electrically insulating layer at its end sections and is uncovered in its central section. As a result of the surface of the at least one nanotube being partly uncovered, the uncovered surface of the nanotube can be used as an active sensor surface. For example, the uncovered surface of the nanotube can come into operative contact with an atmosphere which surrounds the nanotube array. The electrical resistance of a nanotube changes significantly in the presence of certain gases. Thus because the nanotube is clear and uncovered, the nanotube array can be used in many sensor applications.
摘要翻译：纳米管阵列及其制造方法。纳米管阵列具有衬底，催化剂层，其包括在衬底的表面上的一个或多个子区域，和布置在催化剂层表面上的平行于衬底表面的至少一个纳米管。所述至少一个纳米管平行于衬底的表面布置，导致至少一个纳米管的平面布置。因此，本发明的纳米管阵列适用于与传统的硅微电子耦合。因此，根据本发明，可以将纳米管阵列电连接到宏观半导体电子器件。此外，根据本发明的纳米管阵列可以在衬底和催化剂层之间具有电绝缘层。该电绝缘层优选地具有使得至少一个纳米管在其端部部分处于电绝缘层上并且在其中心部分未被覆盖的形貌。由于至少一个纳米管的表面部分未被覆盖，纳米管的未被覆盖的表面可以用作主动传感器表面。例如，纳米管的未覆盖表面可以与围绕纳米管阵列的气氛进行操作接触。在某些气体的存在下，纳米管的电阻显着变化。因此，由于纳米管是透明和未覆盖的，所以纳米管阵列可用于许多传感器应用中。

10. 发明申请

US20060175666A1 Integrated circuit arrangement with low-resistance contacts and method for production thereof 有权
公开(公告)号：US20060175666A1
公开(公告)日：2006-08-10
申请号：US11324803
申请日：2006-01-03
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

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