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1. 发明申请

US20070215986A1 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US20070215986A1
公开(公告)日：2007-09-20
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L23/58 , H01L21/467
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料碳层顶部和设置在第一层顶部的硅层。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

2. 发明授权

US07662721B2 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US07662721B2
公开(公告)日：2010-02-16
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L21/461
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层堆叠包括设置在待图案化层的顶部上的碳层，选自设置在碳层顶部上的SiO 2和SiON中的第一层材料和硅层设置在第一层的顶部。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

3. 发明申请

US20070243707A1 Hard Mask Layer Stack And A Method Of Patterning 审中-公开
标题翻译：硬掩模层堆栈和图案化方法
公开(公告)号：US20070243707A1
公开(公告)日：2007-10-18
申请号：US11686501
申请日：2007-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
IPC分类号： H01L21/44 , G03F1/00 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料碳层顶部和设置在第一层顶部的硅层。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

4. 发明申请

US20060084268A1 Method for production of charge-trapping memory cells 审中-公开
标题翻译：电荷俘获记忆体的制造方法
公开(公告)号：US20060084268A1
公开(公告)日：2006-04-20
申请号：US10967014
申请日：2004-10-15
申请人： Martin Verhoeven
发明人： Martin Verhoeven
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/66833
摘要： An oxide layer, a nitride layer, and a layer of amorphous silicon are applied to a surface of a semiconductor substrate. A resist mask is applied and implantations are performed to form doped regions of source and drain and doped regions within the amorphous silicon layer. The resist mask and undoped parts of the amorphous silicon are removed to form a silicon mask. The silicon mask is applied to etch back the nitride layer. After a removal of the silicon mask, the nitride is oxidized to form an oxide-nitride-oxide layer sequence, which is laterally restricted to the area above the source/drain regions.
摘要翻译：将氧化物层，氮化物层和非晶硅层施加到半导体衬底的表面。施加抗蚀剂掩模并进行注入以在非晶硅层内形成源极和漏极以及掺杂区域的掺杂区域。去除抗蚀剂掩模和非晶硅的未掺杂部分以形成硅掩模。硅掩模被施加以蚀刻氮化物层。在去除硅掩模之后，氮化物被氧化以形成氧化物 - 氮化物 - 氧化物层序列，其横向限于源极/漏极区域上方的区域。

5. 发明申请

US20060071259A1 Charge-trapping memory cell and charge-trapping memory device 有权
标题翻译：电荷捕获存储单元和电荷俘获存储器件
公开(公告)号：US20060071259A1
公开(公告)日：2006-04-06
申请号：US10952707
申请日：2004-09-29
申请人： Martin Verhoeven
发明人： Martin Verhoeven
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , G11C16/0475 , H01L21/76895 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/66795 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： The memory cell is arranged in a ridge of semiconductor material forming a fin with sidewalls and a channel region between source and drain regions. Memory layer sequences provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes. This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.
摘要翻译：存储单元布置在半导体材料的脊中，形成具有侧壁和在源极和漏极区之间的沟道区的鳍。提供用于电荷俘获的存储层序列被施加到侧壁，并且栅电极被布置在脊的两侧。在彼此平行的距离处并且具有面向相邻脊的侧壁的多个脊形成电荷捕获存储单元的阵列。字线布置在脊之间，形成栅电极的字线的部分。这种布置使得能够对单元进行双栅极操作，从而允许在每个单个存储单元结构中存储四位信息。

6. 发明申请

US20060067122A1 Charge-trapping memory cell 审中-公开
标题翻译：电荷俘获记忆体
公开(公告)号：US20060067122A1
公开(公告)日：2006-03-30
申请号：US10952711
申请日：2004-09-29
申请人： Martin Verhoeven
发明人： Martin Verhoeven
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466
摘要： The channel region is slightly elevated with respect to the source and drain regions to form steps in the semiconductor surface, which are covered by a dielectric memory layer sequence provided for charge-trapping, the memory layer sequence comprising a lower confinement layer, a memory layer and an upper confinement layer. Electrons that are accelerated from source to drain are more probably scattered on a straight trajectory, on which they pass the lower confinement layer and are trapped in the memory layer. This memory cell aims at improving the speed of write operations.
摘要翻译：沟道区域相对于源极区和漏极区略微升高，以形成半导体表面中的步骤，其被提供用于电荷俘获的介电存储层序列覆盖，存储层序列包括下约束层，存储层和上限制层。从源极到漏极加速的电子更可能散布在直线轨迹上，它们通过下限制层并被捕获在存储层中。该存储单元旨在提高写入操作的速度。

7. 发明申请

US20080061338A1 Method for Processing a Structure of a Semiconductor Component, and Structure in a Semiconductor Component 审中-公开
标题翻译：用于处理半导体部件的结构的方法以及半导体部件中的结构
公开(公告)号：US20080061338A1
公开(公告)日：2008-03-13
申请号：US11851162
申请日：2007-09-06
申请人： Ludovic Lattard , Christoph Noelscher , Martin Verhoeven
发明人： Ludovic Lattard , Christoph Noelscher , Martin Verhoeven
IPC分类号： H01L27/108 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L27/10844 , H01L27/11568
摘要： A method is used for processing a structure of a semiconductor component. The structure has at least one partial structure to be etched, in particular a sublithographic partial structure. The at least one partial structure has at least one structure to be etched with at least one lateral etch stop to which at least one mask is applied in such a way that at least one lateral etch stop is covered by the mask and afterward at least one of the structures to be etched is etched away isotropically as far as at least one etch stop using the mask. The at least one mask and the at least one etch stop are then removed.
摘要翻译：一种用于处理半导体部件的结构的方法。该结构具有至少一个待蚀刻的部分结构，特别是亚光刻部分结构。所述至少一个部分结构具有至少一个要被蚀刻的结构，至少一个横向蚀刻停止件，至少一个掩模被施加到至少一个掩模，使得至少一个横向蚀刻停止物被掩模覆盖，然后至少一个的待蚀刻结构被各向同性地蚀刻到使用掩模的至少一个蚀刻停止。然后去除至少一个掩模和至少一个蚀刻停止部。

8. 发明授权

US07095078B2 Charge trapping memory cell 有权
标题翻译：电荷捕获存储单元
公开(公告)号：US07095078B2
公开(公告)日：2006-08-22
申请号：US10954156
申请日：2004-09-29
申请人： Martin Verhoeven
发明人： Martin Verhoeven
IPC分类号： H01L29/792
CPC分类号： G11C16/0475 , H01L27/112 , H01L29/7923
摘要： In a charge trapping memory cell, programming occurs by trapping hot electrons from the channel region in a storage layer. The erasure occurs by Fowler-Nordheim tunneling of the electrons through the lower boundary layer to source or drain or preferably through the upper boundary layer into the gate electrode. The boundary layers are preferably aluminum oxide.
摘要翻译：在电荷捕获存储单元中，通过从存储层中的沟道区捕获热电子来进行编程。这种擦除是由Fowler-Nordheim通过下边界层将电子穿透到源极或漏极，或者优选通过上边界层进入栅电极。边界层优选为氧化铝。

9. 发明申请

US20050117135A1 Method and imaging apparatus for imaging a structure onto a semiconductor wafer by means of immersion lithography 有权
标题翻译：用于通过浸没式光刻将结构成像到半导体晶片上的方法和成像装置
公开(公告)号：US20050117135A1
公开(公告)日：2005-06-02
申请号：US10986288
申请日：2004-11-12
申请人： Martin Verhoeven , Thomas Zell
发明人： Martin Verhoeven , Thomas Zell
IPC分类号： G03B27/52 , G03F7/20 , G03F7/22
CPC分类号： G03F7/70075 , G03B27/52 , G03F7/70091 , G03F7/70341
摘要： The hydrodynamic effects—which occur during immersion lithography as a result of the movement of the semiconductor wafer—in a liquid preferably provided between the last lens surface of the projection system and the semiconductor wafer can be avoided by means of a movable illumination region for illuminating a cutout of a mask containing a structure to that can be imaged onto the semiconductor wafer. A scan movement of the mask and the semiconductor wafer can be either reduced or entirely avoided by means of a movement of the illumination region.
摘要翻译：作为半导体晶片移动的结果，在优选设置在投影系统的最后一个透镜表面之间的液体和半导体晶片之间的液体中的流体动力学效应可以通过用于照明的可移动照明区域来避免包含可以成像到半导体晶片上的结构的掩模的切口。可以通过照明区域的移动来减少或完全避免掩模和半导体晶片的扫描移动。

10. 发明授权

US07224439B2 Method and imaging apparatus for imaging a structure onto a semiconductor wafer by means of immersion lithography 有权
标题翻译：用于通过浸没式光刻将结构成像到半导体晶片上的方法和成像装置
公开(公告)号：US07224439B2
公开(公告)日：2007-05-29
申请号：US10986288
申请日：2004-11-12
申请人： Martin Verhoeven , Thomas Zell
发明人： Martin Verhoeven , Thomas Zell
IPC分类号： G03B27/43
CPC分类号： G03F7/70075 , G03B27/52 , G03F7/70091 , G03F7/70341
摘要： The hydrodynamic effects—which occur during immersion lithography as a result of the movement of the semiconductor wafer—in a liquid preferably provided between the last lens surface of the projection system and the semiconductor wafer can be avoided by means of a movable illumination region for illuminating a cutout of a mask containing a structure to that can be imaged onto the semiconductor wafer. A scan movement of the mask and the semiconductor wafer can be either reduced or entirely avoided by means of a movement of the illumination region.
摘要翻译：作为半导体晶片移动的结果，在优选设置在投影系统的最后一个透镜表面之间的液体和半导体晶片之间的液体中的流体动力学效应可以通过用于照明的可移动照明区域来避免包含可以成像到半导体晶片上的结构的掩模的切口。可以通过照明区域的移动来减少或完全避免掩模和半导体晶片的扫描移动。

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