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1. 发明申请

US20080197394A1 METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20080197394A1
公开(公告)日：2008-08-21
申请号：US11676635
申请日：2007-02-20
申请人： Dirk Caspary , Arnd Scholz , Stefano Parascandola , Christoph Noelscher
发明人： Dirk Caspary , Arnd Scholz , Stefano Parascandola , Christoph Noelscher
IPC分类号： H01L29/94 , G03F1/00 , H01L21/311 , H01L27/108
CPC分类号： H01L21/3086 , H01L21/3088 , H01L27/0207 , H01L27/1087 , H01L27/115
摘要： A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.
摘要翻译：公开了制造半导体结构的方法。在一个实施例中，在衬底上方提供第一掩模。第一掩模包括沿着第一轴线延伸的第一掩模线。在第一掩模上方提供第二掩模。第二掩模包括沿着与第一轴相交的第二轴延伸的第二掩模线。第一和第二掩模中的至少一个由音调分段方法形成。可以在衬底中形成结构，其中第一和第二掩模作为组合掩模是有效的。结构可以在重复线结构的最小光刻特征尺寸的范围内以间距等间隔。

2. 发明申请

US20070215986A1 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US20070215986A1
公开(公告)日：2007-09-20
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L23/58 , H01L21/467
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料碳层顶部和设置在第一层顶部的硅层。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

3. 发明申请

US20070026684A1 Method of producing pitch fractionizations in semiconductor technology 有权
$Method of producing pitch fractionizations in semiconductor technology$
标题翻译：在半导体技术中制备节距分级的方法
公开(公告)号：US20070026684A1
公开(公告)日：2007-02-01
申请号：US11194489
申请日：2005-08-01
申请人： Stefano Parascandola , Dirk Caspary
发明人： Stefano Parascandola , Dirk Caspary
IPC分类号： H01L21/311 , H01L21/461 , B44C1/22
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Spacers are formed on sidewalls of striplike parts of a pattern layer of periodic structure. The pattern layer is removed, and the spacers are covered with a further spacer layer, which is then structured to second sidewall spacers. Gaps between the spacers are filled with a complementary layer. The upper surface is planarized to a lower surface level, leaving a periodic succession of the first spacers, the second spacers and the residual parts of the complementary layer. The lateral dimensions are adapted in such a manner that a removal of one or two of the remaining layers renders a periodic pattern of smaller pitch.
摘要翻译：间隔物形成在周期性结构的图案层的带状部分的侧壁上。去除图案层，并且间隔物被另外的间隔层覆盖，然后隔离层被构造成第二侧壁间隔物。间隔物之间的间隙填充有互补层。上表面被平坦化到较低的表面水平，留下第一间隔物，第二间隔物和互补层的残留部分的周期性连续。横向尺寸以这样一种方式进行调整，使得一个或两个剩余的层的移除呈现较小间距的周期性图案。

4. 发明授权

US07642158B2 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07642158B2
公开(公告)日：2010-01-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

5. 发明申请

US20070243707A1 Hard Mask Layer Stack And A Method Of Patterning 审中-公开
标题翻译：硬掩模层堆栈和图案化方法
公开(公告)号：US20070243707A1
公开(公告)日：2007-10-18
申请号：US11686501
申请日：2007-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
IPC分类号： H01L21/44 , G03F1/00 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料碳层顶部和设置在第一层顶部的硅层。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

6. 发明申请

US20070212892A1 Method of forming semiconductor device structures using hardmasks 审中-公开
标题翻译：使用硬掩模形成半导体器件结构的方法
公开(公告)号：US20070212892A1
公开(公告)日：2007-09-13
申请号：US11588429
申请日：2006-10-27
申请人： Dirk Caspary , Stefano Parascandola
发明人： Dirk Caspary , Stefano Parascandola
IPC分类号： H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338
摘要： A first hardmask layer is provided over a substrate, and a second hardmask layer is provided over the first hardmask layer. The second hardmask layer is patterned to form a second hardmask structure having sidewalls. A sacrificial layer of a sacrificial material is conformally deposited such that the deposited sacrificial layer has substantially horizontal and vertical portions. The horizontal portions of the sacrificial layer are removed to form lines of the sacrificial material adjacent to the sidewalls of the second hardmask lines. The sacrificial layer is at least partially removed to structure the sacrificial material and the remaining sacrificial layer is used to structure the first hardmask. The second hardmask structures is removed to uncover portions of the first hardmask. Uncovered portions of the substrate are etched, thereby forming structures in the substrate below the first hardmask.
摘要翻译：在衬底上提供第一硬掩模层，并且在第一硬掩模层上提供第二硬掩模层。图案化第二硬掩模层以形成具有侧壁的第二硬掩模结构。牺牲材料的牺牲层被共形沉积，使得沉积的牺牲层具有基本水平和垂直的部分。去除牺牲层的水平部分以形成与第二硬掩模线的侧壁相邻的牺牲材料的线。至少部分去除牺牲层以构造牺牲材料，并且使用剩余的牺牲层来构造第一硬掩模。移除第二硬掩模结构以露出第一硬掩模的部分。对衬底的未覆盖部分进行蚀刻，从而在第一硬掩模下面的衬底中形成结构。

7. 发明申请

US20070210449A1 Memory device and an array of conductive lines and methods of making the same 审中-公开
标题翻译：存储器件和导线阵列及其制造方法
公开(公告)号：US20070210449A1
公开(公告)日：2007-09-13
申请号：US11369013
申请日：2006-03-07
申请人： Dirk Caspary , Stefano Parascandola
发明人： Dirk Caspary , Stefano Parascandola
IPC分类号： H01L23/48
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052 , H01L2924/0002 , H01L2924/00
摘要： An array of conductive lines is formed on or at least partially in a semiconductor substrate. The array includes a number of conductive lines extending in a first direction, a number of landing pads made of a conductive material, with individual landing pads being connected to corresponding ones of the conductive lines, wherein the conductive lines include first and second subsets of conductive lines. The conductive lines of the first subset alternate with the conductive lines of the second subset, wherein the landing pads connected to the conductive lines of the first subset are disposed on a first side of the conductive lines, and the landing pads connected to the conductive lines of the second subset are disposed on a second side of the conductive lines, the first side being opposite to the second side.
摘要翻译：导电线阵列形成在半导体衬底上或至少部分地形成在半导体衬底中。阵列包括沿着第一方向延伸的多条导电线，多个由导电材料制成的着陆焊盘，各个着陆焊盘连接到对应的导线，其中导线包括第一和第二导电子集线条。第一子集的导线与第二子集的导线交替，其中连接到第一子集的导线的着陆焊盘设置在导线的第一侧上，并且连接到导线的着陆焊盘所述第二子集的第二侧布置在所述导电线的第二侧上，所述第一侧与所述第二侧相对。

8. 发明申请

US20070158688A1 Memory device and a method of forming a memory device 有权
标题翻译：存储装置和形成存储装置的方法
公开(公告)号：US20070158688A1
公开(公告)日：2007-07-12
申请号：US11327054
申请日：2006-01-06
申请人： Dirk Caspary , Stefano Parascandola
发明人： Dirk Caspary , Stefano Parascandola
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/10 , H01L27/105 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of the first conductive lines having a distance bs from each other. Each of the second conductive lines has a line width wl and two neighboring ones of the second conductive lines having a distance ws from each other. Each memory cell is accessible by addressing corresponding ones of said first and second conductive lines. Each of the landing pads are made of a conductive material and are connected with a corresponding one of said second conductive lines. Each of said landing pads has a width wp and length lp and the line width wl of each of the second conductive lines is larger than the distance ws and the width wp of each of the landing pads is larger than the line width wl and the length lp of each of the landing pads is larger than the line width wl.
摘要翻译：存储器件包括具有表面，多个第一和第二导电线，多个存储单元和多个着陆焊盘的半导体衬底。每个第一导线具有线宽度wb和彼此之间具有距离bs的第一导线中的两个相邻的导线。每个第二导线具有线宽w1和彼此之间具有距离ws的两条相邻的第二导线。通过寻址所述第一和第二导线中相应的一个可访问每个存储单元。每个着陆焊盘由导电材料制成并且与相应的所述第二导电线连接。每个所述着陆焊盘具有宽度wp和长度lp，并且每个第二导线的线宽w1大于距离ws，并且每个着陆焊盘的宽度wp大于线宽w1和长度每个着陆垫的lp大于线宽w1。

9. 发明申请

US20070075381A1 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070075381A1
公开(公告)日：2007-04-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

10. 发明申请

US20070075335A1 Semiconductor memory device and method of production 有权
公开(公告)号：US20070075335A1
公开(公告)日：2007-04-05
申请号：US11241820
申请日：2005-09-30
申请人： Dirk Caspary , Stefano Parascandola
发明人： Dirk Caspary , Stefano Parascandola
IPC分类号： H01L27/10
CPC分类号： H01L27/10 , H01L27/105 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： Final sections of the word lines are arranged in a staggered fashion to fan out and have larger lateral extensions than the word lines. Interspaces are filled with a dielectric material, and a mask is applied that partially covers the final sections and leaves contact areas in regions adjacent to the final sections and to the interspaces open. This mask is used to remove the dielectric material between the word line stacks. A second word line layer is applied and planarized to form second word lines between the first word lines, which have contact areas arranged in a staggered fashion to fan out like the final sections of the first word lines.

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