专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6058066A Enhanced register array accessible by both a system microprocessor and a wavetable audio synthesizer 有权
标题翻译：增强的寄存器阵列可由系统微处理器和波形音频合成器访问
公开(公告)号：US6058066A
公开(公告)日：2000-05-02
申请号：US160992
申请日：1998-09-25
申请人： David E. Norris , Larry D. Hewitt , Jeffrey M. Blumenthal
发明人： David E. Norris , Larry D. Hewitt , Jeffrey M. Blumenthal
IPC分类号： G06F3/16 , G06F7/02 , G06F9/38 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K23/68 , H03M3/02 , H03M7/32 , G11C8/00
CPC分类号： H03K23/68 , G06F3/162 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.
摘要翻译：一种可由PC音频电路的系统微处理器和数字信号处理器访问的寄存器阵列，包括：（i）具有连接到数字信号处理器输入/输出端口的第一端口的随机存取存储器（RAM），以及第二端口连接到RAM输入/输出端口; （ii）连接到RAM输入/输出端口并具有到寄存器数据总线的连接的寄存器数据端口; （iii）用于定时寄存器阵列操作的定时电路; （iv）用于分别在所述RAM中选择行和列的行和列选择电路; 和（v）连接到所述定时电路的输入/输出通道就绪信号线。 RAM包括多个边沿位，每个边沿位存储指示存储在所述RAM中的一行数据值的处理是处于活动还是非活动状态的值。当RAM不空闲或微处理器寻求访问当前受数字信号处理器访问的RAM的一行时，系统微处理器被禁止访问RAM。如果微处理器禁止向RAM写入数据，则数据可能会临时存储在寄存器数据端口中，直到微处理器的访问被使能为止。

2. 发明授权

US06272465B1 Monolithic PC audio circuit 失效
标题翻译：单片PC音频电路
公开(公告)号：US06272465B1
公开(公告)日：2001-08-07
申请号：US08934969
申请日：1997-09-22
申请人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G10L500
CPC分类号： H03K23/68 , G06F3/162 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.
摘要翻译：用于在个人计算机中提供增强音频性能的单片集成电路。单片电路包括波形合成器; 全功能立体声编解码电路，包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

3. 发明授权

US5659466A Monolithic PC audio circuit with enhanced digital wavetable audio synthesizer 失效
公开(公告)号：US5659466A
公开(公告)日：1997-08-19
申请号：US333536
申请日：1994-11-02
申请人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

4. 发明授权

US07983181B1 Technique for negotiating a width of a packet-based communication link 有权
标题翻译：用于协商基于分组的通信链路的宽度的技术
公开(公告)号：US07983181B1
公开(公告)日：2011-07-19
申请号：US11379866
申请日：2006-04-24
申请人： Paul Miranda , Larry D. Hewitt
发明人： Paul Miranda , Larry D. Hewitt
IPC分类号： H04L12/26
CPC分类号： H03M13/09 , H04L1/0061 , H04L25/14
摘要： A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link having a width of N or multiple sublinks having a width less than N based on a respective value of the respective signal on the one or more control lines.
摘要翻译：用于协商第一设备和第二设备之间的链路的宽度的技术包括在初始化期间检测与N位链路的至少一部分相关联的一个或多个控制线上的相应信号。基于一个或多个控制线上的相应信号的相应值，将N位链路配置为宽度为N的单个链路或宽度小于N的多个子链路。

5. 发明授权

US07146510B1 Use of a signal line to adjust width and/or frequency of a communication link during system operation 有权
标题翻译：在系统运行期间使用信号线来调整通信链路的宽度和/或频率
公开(公告)号：US07146510B1
公开(公告)日：2006-12-05
申请号：US10198637
申请日：2002-07-18
申请人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
发明人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.
摘要翻译：集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有集成电路进入复位状态。宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

6. 发明授权

US06725297B1 Peripheral interface circuit for an I/O node of a computer system 有权
标题翻译：用于计算机系统的I / O节点的外围接口电路
公开(公告)号：US06725297B1
公开(公告)日：2004-04-20
申请号：US10093146
申请日：2002-03-07
申请人： Tahsin Askar , Larry D. Hewitt , Eric G. Chambers
发明人： Tahsin Askar , Larry D. Hewitt , Eric G. Chambers
IPC分类号： G06F1300
CPC分类号： G06F13/128
摘要： A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.
摘要翻译：用于计算机系统的I / O节点的外围接口电路。一种用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路，第二缓冲电路和总线接口电路。第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线上传输的命令。

7. 发明授权

US06697890B1 I/O node for a computer system including an integrated I/O interface 有权
标题翻译：包含集成I / O接口的计算机系统的I / O节点
公开(公告)号：US06697890B1
公开(公告)日：2004-02-24
申请号：US10034878
申请日：2001-12-27
申请人： Dale E. Gulick , Larry D. Hewitt
发明人： Dale E. Gulick , Larry D. Hewitt
IPC分类号： G06F1312
CPC分类号： G06F13/4247 , G06F13/4004
摘要： An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.
摘要翻译：一个包含集成I / O接口的计算机系统的I / O节点。在集成电路上实现的用于计算机系统的输入/输出节点包括第一收发器单元，第二收发器单元，分组隧道，桥接单元和I / O接口单元。第一收发器单元可以在分组总线的第一链路上接收和发送分组事务。第二收发器单元可以在分组总线的第二链路上接收和发送分组事务。分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。桥接单元可以接收来自第一收发器的特定分组事务可以在外围总线上发送与特定分组事务相对应的事务。 I / O接口单元可以从第一收发器单元接收附加分组事务，并且可以在I / O链路上传送与附加分组事务相对应的事务。

8. 发明授权

US06385705B1 Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system 有权
公开(公告)号：US06385705B1
公开(公告)日：2002-05-07
申请号：US09702147
申请日：2000-10-30
申请人： James B. Keller , Dale E. Gulick , Larry D. Hewitt , Geoffrey Strongin
发明人： James B. Keller , Dale E. Gulick , Larry D. Hewitt , Geoffrey Strongin
IPC分类号： G06F1300
CPC分类号： G06F13/1621
摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

9. 发明授权

US06202116B1 Write only bus with whole and half bus mode operation 失效
标题翻译：只用总线和半总线模式运行总线
公开(公告)号：US06202116B1
公开(公告)日：2001-03-13
申请号：US09098876
申请日：1998-06-17
申请人： Larry D. Hewitt
发明人： Larry D. Hewitt
IPC分类号： G06F1300
CPC分类号： G06F13/4273
摘要： A data bus is divided into two portions. One portion of the bus transfers data from one side of the bus to the other and the other portion of the bus transfers data in the opposite direction. Bus cycles that originate from one side of the bus only go in one direction (from the originator to the other side). In order to avoid inefficiency because one of the portions of the bus may become unused if a long bus cycle is going in one direction while nothing is being transferred in the opposite direction, one side can take over the whole data bus and transfer data over both sides of the bus.
摘要翻译：数据总线分为两部分。总线的一部分将数据从总线的一侧传输到另一侧，而总线的另一部分以相反的方向传输数据。从总线一侧起始的总线循环只能沿一个方向（从始发者到另一方）。为了避免低效率，因为如果长的总线周期在一个方向上进行而总线周期不会在相反的方向上传输，总线的一部分可能会变得不用，则一侧可以接管整个数据总线并且通过两者传输数据公车两边。

10. 发明授权

US07334123B2 Computer system including a bus bridge for connection to a security services processor 失效
标题翻译：计算机系统包括用于连接到安全服务处理器的总线桥
公开(公告)号：US07334123B2
公开(公告)日：2008-02-19
申请号：US10429132
申请日：2003-05-02
申请人： Dale E. Gulick , Geoffrey S. Strongin , Larry D. Hewitt
发明人： Dale E. Gulick , Geoffrey S. Strongin , Larry D. Hewitt
IPC分类号： H04L9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F21/74 , G06F21/85 , G06F2221/2105
摘要： A computer system including a bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor. The bus bridge may include a transaction source detector, a configuration header and control logic. The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus. The control logic may also cause the configuration header to be accessible during a boot-up sequence in response to determining that the security services processor is coupled to the non-enumerable, peripheral bus.
摘要翻译：一种计算机系统，包括用于桥接安全执行模式处理器和安全服务处理器之间的事务的总线桥。总线桥可以包括事务源检测器，配置头和控制逻辑。事务源检测器可以接收由于执行安全初始化指令而执行的安全初始化事务。此外，事务源检测器可以确定安全执行模式处理器是否是安全初始化事务的源。配置头可以提供与安全服务处理器相关联的信息的存储。控制逻辑可以确定安全服务处理器是否经由不可枚举的外围总线耦合到总线桥。响应于确定安全服务处理器耦合到不可枚举的外围总线，控制逻辑还可以使得配置头在引导序列期间可访问。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式