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1. 发明授权

US07146510B1 Use of a signal line to adjust width and/or frequency of a communication link during system operation 有权
标题翻译：在系统运行期间使用信号线来调整通信链路的宽度和/或频率
公开(公告)号：US07146510B1
公开(公告)日：2006-12-05
申请号：US10198637
申请日：2002-07-18
申请人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
发明人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.
摘要翻译：集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有集成电路进入复位状态。宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

2. 发明授权

US07174467B1 Message based power management in a multi-processor system 有权
标题翻译：多处理器系统中基于消息的电源管理
公开(公告)号：US07174467B1
公开(公告)日：2007-02-06
申请号：US10185171
申请日：2002-06-28
申请人： Frank P. Helms , Dale E. Gulick , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
发明人： Frank P. Helms , Dale E. Gulick , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
IPC分类号： G06F1/26 , G06F1/28 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/172
摘要： A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.
摘要翻译：利用基于消息的电源管理方法为多处理器系统提供电源管理。在多处理器系统的一个处理器上通过输入/输出通信链路接收功率管理消息，该输入/输出通信链路为多处理器系统的处理器提供输入/输出接入。电源管理消息包括对多处理器系统的处理器编码电源管理状态的电源管理字段。通过输入/输出通信链路接收电力管理消息的处理器通过编码电源管理状态的一个或多个处理器间通信链路向多处理器系统中的其他处理器发送电源管理消息。

3. 发明授权

US07051218B1 Message based power management 有权
标题翻译：基于消息的电源管理
公开(公告)号：US07051218B1
公开(公告)日：2006-05-23
申请号：US10185195
申请日：2002-06-28
申请人： Dale E. Gulick , Frank P. Helms , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
发明人： Dale E. Gulick , Frank P. Helms , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
IPC分类号： G06F1/30 , G06F3/00 , G06F13/36
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.
摘要翻译：基于消息的电力管理系统将用于电力管理的传统信号和用于区分电力状态的其他信号转换成通过通信链路发送的消息。在通信链路上发送的系统消息包括对接收系统消息的设备的电源管理级进行编码的字段。此外，与通信链路分离的一个或多个附加信号可以用于指示何时在接收到电力管理消息之后采取行动。

4. 发明授权

US06557048B1 Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof 有权
标题翻译：实现用于在其相干部分内对输入/输出（IO）存储器操作进行排序的系统和方法的计算机系统
公开(公告)号：US06557048B1
公开(公告)日：2003-04-29
申请号：US09431364
申请日：1999-11-01
申请人： James B. Keller , Derrick R. Meyer , Dale E. Gulick , Larry D. Hewitt
发明人： James B. Keller , Derrick R. Meyer , Dale E. Gulick , Larry D. Hewitt
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge. The I/O node may, for example, produce and/or provide a first transaction followed by a second transaction. The host bridge may dispatch the second transaction with respect to the first transaction according to a predetermined set of ordering rules. For example, the host bridge may: (i) receive the first and second transactions, (ii) dispatch the first transaction within the processing subsystem, and (iii) dispatch the second transaction within the processing subsystem dependent upon progress of the first transaction within the processing subsystem and the predetermined set of ordering rules.
摘要翻译：提出了一种实现用于排序输入/输出（I / O）存储器操作的系统和方法的计算机系统。在一个实施例中，计算机系统包括处理子系统和I / O子系统。处理子系统包括通过相干通信链路互连的多个处理节点。每个处理节点可以包括执行软件指令的处理器。 I / O子系统包括通过非相干通信链路串联耦合的一个或多个I / O节点。每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。其中一个处理节点包括一个主机桥，它转换在处理子系统和I / O子系统之间移动的数据包。其中一个I / O节点耦合到包括主机桥的处理节点。耦合到处理节点的I / O节点产生和/或提供具有处理子系统内包含主机桥的处理节点的目的地或目标的事务。 I / O节点可以例如产生和/或提供第一事务，随后是第二事务。主桥可以根据预定的一组排序规则来分派关于第一事务的第二事务。例如，主桥可以：（i）接收第一和第二事务，（ii）在处理子系统内调度第一事务，以及（iii）根据第一事务的进度在处理子系统内调度第二事务处理子系统和预定的一套排序规则。

5. 发明授权

US07093105B2 Method and apparatus for determining availability of a queue to which a program step is issued out of program order 有权
标题翻译：用于确定从程序顺序发出程序步骤的队列的可用性的方法和装置
公开(公告)号：US07093105B2
公开(公告)日：2006-08-15
申请号：US10779503
申请日：2004-02-13
申请人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
IPC分类号： G06F9/30
CPC分类号： G06F7/76 , G06F7/4824 , G06F7/508 , G06F7/535 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F2207/5352
摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.
摘要翻译：允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。该方法使用附加位来表示模块结果（值），并且还可以利用加载存储器号映射存储器来增加执行速度。通过这样的布置，由于等待当前指令的所需资源（即，存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是下一个在原程序中。因此，本发明允许存储器参考指令在资源可用时发布。

6. 发明授权

US06760838B2 System and method of initializing and determining a bootstrap processor [BSP] in a fabric of a distributed multiprocessor computing system 有权
标题翻译：在分布式多处理器计算系统的结构中初始化和确定引导处理器[BSP]的系统和方法
公开(公告)号：US06760838B2
公开(公告)日：2004-07-06
申请号：US09773763
申请日：2001-01-31
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
IPC分类号： G06F15177
CPC分类号： G06F15/177
摘要： A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed. This scheme includes designating a bootstrap processor, locating the boot ROM, establishing the manner in which the devices are interconnected, and defining routing directions for routing communications among the various devices in the computing system.
摘要翻译：提供了一种用于初始化包括在包括多个独立点对点链路的通信链路上通信的多个设备的计算系统的方法，每个点对点链路互连所述多个设备中的相应对。该方法包括链路初始化过程，其包括首先使用包括公共频率和公共链路宽度的公共通信参数在每个互连链路上配置每个相应设备对进行通信。链路初始化过程还可以包括用于确定每个互连的设备对的最大通信参数的优化过程。如果最大兼容参数与任何设备对的公共参数不同，则可以使用最大兼容参数将该对设备重新配置为在互连链路上进行通信。一旦建立了通信能力，就可以执行用于计算机系统的一个或多个通信结构的建立。该方案包括指定引导处理器，定位引导ROM，建立设备互连的方式，以及定义用于在计算系统中的各种设备之间路由通信的路由选择方向。

7. 发明授权

US06738896B1 Method and apparatus for determining availability of a queue which allows random insertion 失效
标题翻译：用于确定允许随机插入的队列的可用性的方法和装置
公开(公告)号：US06738896B1
公开(公告)日：2004-05-18
申请号：US09495190
申请日：2000-01-31
申请人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
IPC分类号： G06F930
CPC分类号： G06F7/76 , G06F7/4824 , G06F7/508 , G06F7/535 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F2207/5352
摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (valve) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.
摘要翻译：允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。该方法使用额外的位来表示模块结果（阀），并且还可以利用加载存储器号码映射存储器来增加执行速度。通过这样的布置，由于等待当前指令的所需资源（即存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是下一个在原程序中。因此，本发明允许存储器参考指令在资源可用时发布。

8. 发明授权

US06505261B1 System and method for initiating an operating frequency using dual-use signal lines 有权
标题翻译：使用双用途引脚启动工作频率的系统和方法
公开(公告)号：US06505261B1
公开(公告)日：2003-01-07
申请号：US09428633
申请日：1999-10-27
申请人： Derrick R. Meyer , Philip Enrique Madrid
发明人： Derrick R. Meyer , Philip Enrique Madrid
IPC分类号： G06F104
CPC分类号： G06F13/4059
摘要： A system and method for inputting a set of values, e.g. an operating frequency, using dual-use signal connections. In an exemplary computer system, one or more processors are each coupled to a bridge. The dual-use signal connections are used to input an operating frequency ratio to a processor. The operating frequency ratio may also be input to the bridge. Once the operation of the processor has been initialized, the dual-use signal connections may be used to output operating parameters of the processor. The use of the using dual-use signal connections may advantageously allow for the operating frequency ratio to be input to the processor without dedicated signal lines or pins.
摘要翻译：一种用于输入一组值的系统和方法，例如一个工作频率，使用两用信号连接。在示例性计算机系统中，一个或多个处理器各自耦合到桥。双用途信号连接用于向处理器输入工作频率比。工作频率比也可以输入到桥。一旦处理器的操作被初始化，则可以使用双重用途信号连接来输出处理器的操作参数。使用使用双重用途信号连接可以有利地允许将工作频率比率输入到处理器，而无需专用信号线或引脚。

9. 发明授权

US06360314B1 Data cache having store queue bypass for out-of-order instruction execution and method for same 失效
标题翻译：具有存储队列旁路的数据高速缓存用于无序指令执行及其方法
公开(公告)号：US06360314B1
公开(公告)日：2002-03-19
申请号：US09115186
申请日：1998-07-14
申请人： David Arthur James Webb, Jr. , James B. Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James B. Keller , Derrick R. Meyer
IPC分类号： G06F938
CPC分类号： G06F9/3834 , G06F9/3826
摘要： A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction. The bypass mechanism also operates in cases in which multiple prior stores to the same address are pending when a load that needs to read that address issues.
摘要翻译：公开了一种用于执行装载和存储指令的计算机系统的旁路机构。旁路机制将每个发布加载指令的地址与尚未更新内存的一组最近的存储指令进行比较。最近的商店的匹配提供了加载数据，而不是从内存中检索数据。商店队列持有最近发布的商店。每个存储队列条目和发布加载包括数据大小指示符。在数据旁路之后，将发布负载的数据大小指示符与匹配存储队列条目的数据大小指示符进行比较。当发布负载的数据大小指示符与匹配的存储队列条目的数据大小指示符不同时，用信号通知陷阱。陷阱信号表示旁路机构提供的数据不足以满足加载指令的要求。在需要读取该地址的负载发生问题的情况下，旁路机制还可以在多个先前存储到同一地址的情况下进行操作。

10. 发明授权

US06253304B1 Collation of interrupt control devices 有权
标题翻译：中断控制装置的整理
公开(公告)号：US06253304B1
公开(公告)日：2001-06-26
申请号：US09224821
申请日：1999-01-04
申请人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
发明人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
IPC分类号： G06F946
CPC分类号： G06F9/4812
摘要： A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.
摘要翻译：第一和第二局部中断控制器设置在单个集成电路上。第一和第二局部中断控制器被耦合以可分别地向第一和第二处理器提供至少一个中断请求信号。输入/输出（I / O）中断控制器也在集成电路上并被耦合以从至少一个输入/输出设备接收中断请求。集成电路上的通信电路耦合到输入/输出中断控制器和第一和第二本地中断控制器。通信电路提供第一局部中断控制器，第二局部中断控制器和输入/输出中断控制器之间的中断信息传输。

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