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1. 发明授权

US10601427B1 Clock generating device and clock generating method 有权
公开(公告)号：US10601427B1
公开(公告)日：2020-03-24
申请号：US16508495
申请日：2019-07-11
申请人： Realtek Semiconductor Corporation
发明人： Chia-Kuei Hsu , Ming-Kai Chuang , Mei-Chuan Lu
IPC分类号： H03K23/68 , H03L7/081 , H03K19/20
摘要： A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.

2. 发明授权

US10425091B2 Fractional clock generator 有权
公开(公告)号：US10425091B2
公开(公告)日：2019-09-24
申请号：US16151752
申请日：2018-10-04
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Dinesh Jain , Markus Friedrich Dietl
IPC分类号： H03L7/06 , H03L7/197 , H03K23/68
摘要： A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a ΣΔ modulator and a summer to utilize an input N.α control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or β value of the full quadrant analog interpolator.

3. 发明授权

US10177773B2 Programmable clock divider 有权
公开(公告)号：US10177773B2
公开(公告)日：2019-01-08
申请号：US15297537
申请日：2016-10-19
申请人： STMicroelectronics International N.V.
发明人： Nitin Gupta , Jeet Narayan Tiwari
IPC分类号： H03K21/00 , H03K23/00 , H03L7/197 , H03K19/20 , H03K21/10 , H03K23/70 , H03K23/66 , H03K23/68
摘要： In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

4. 发明授权

US09608523B1 Regulator, serializer, deserializer, serializer/deserializer circuit, and method of controlling the same 有权
公开(公告)号：US09608523B1
公开(公告)日：2017-03-28
申请号：US15066563
申请日：2016-03-10
申请人： Kabushiki Kaisha Toshiba
发明人： Takayuki Iwai , Yasushi Shizuki
IPC分类号： H03M9/00 , H02M3/158 , H03L7/08 , H03K21/02 , H04L7/033 , G06F1/08 , H03K7/06 , H04L27/26 , H03K23/68 , G06F1/10
CPC分类号： H03M9/00 , G06F1/08 , G06F1/10 , H03K7/06 , H03K21/02 , H03K23/68 , H03L7/0807 , H04L7/033 , H04L7/0337 , H04L27/2647
摘要： According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

5. 发明授权

US09257991B2 High-speed frequency divider 有权
标题翻译：高速分频器
公开(公告)号：US09257991B2
公开(公告)日：2016-02-09
申请号：US14160201
申请日：2014-01-21
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Ferdinando Pace
IPC分类号： H03K21/00 , H03K23/00 , H03K21/10 , H03K23/40 , H03K23/54 , H03K23/68
CPC分类号： H03K21/10 , H03K23/40 , H03K23/54 , H03K23/68
摘要： A programmable high-speed frequency divider architecture is provided that is programmable to divide an input clock signal frequency by a selectable division N. The frequency divider architecture has a shift register circuit having N/2 shift register stages, connected in series when N is an even integer and trunc[N/2]+1 shift register stages when N is an odd integer. The frequency divider architecture includes a feedback logic circuit that performs a logical NAND of the output clock signal with the logical ORed result of a pre-output signal provided from a shift register stage prior to the output stage and another signal that indicates whether the selectable divisor N is odd or even.
摘要翻译：提供了一种可编程的高速分频器架构，其可编程以通过可选择分段N来分频输入时钟信号频率。分频器架构具有移位寄存器电路，其具有N / 2个移位寄存器级，当N为当N是一个奇整数时，甚至整数和trunc [N / 2] +1个移位寄存器级。分频器架构包括反馈逻辑电路，其在输出级之前从移位寄存器级提供的预输出信号的逻辑或运算结果执行输出时钟信号的逻辑NAND，以及指示是否可选择除数的另一信号 N是奇数或偶数。

6. 发明授权

US09184752B2 Low power digital fractional divider with glitchless output 有权
$Low power digital fractional divider with glitchless output$
标题翻译：低功率数字小数分频器，无故障输出
公开(公告)号：US09184752B2
公开(公告)日：2015-11-10
申请号：US14020239
申请日：2013-09-06
申请人： Synopsys, Inc.
发明人： Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H03K21/02 , H03K23/66 , H03K23/68
CPC分类号： H03K21/023 , H03K23/662 , H03K23/68
摘要： A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.
摘要翻译：描述了将高速数字时钟除以分数值的数字电路。该电路使用分频器电路，并将分频器时钟相移一小段相位，以实现所需的分数除法。使用时钟多路复用器来执行时钟偏移，并且使用屏蔽多路复用器来消除时钟偏移期间的毛刺。

7. 发明授权

US09124278B1 Half rate serialization and memory cell for high speed serializer-deserializer 有权
标题翻译：用于高速串行器 - 解串器的半速率串行化和存储单元
公开(公告)号：US09124278B1
公开(公告)日：2015-09-01
申请号：US14704871
申请日：2015-05-05
申请人： Cadence Design Systems, Inc.
发明人： Tamal Das
IPC分类号： H03M9/00 , G11C8/18 , H03K23/66 , G06F1/08 , H04L7/033 , H03K7/06 , H04L27/26 , G06F1/10 , H03K23/68
CPC分类号： H03M9/00 , G06F1/08 , G06F1/10 , G11C7/222 , G11C27/02 , H03K7/06 , H03K23/667 , H03K23/68 , H04J3/047 , H04J3/0685 , H04L7/0337 , H04L27/2647
摘要： Methods and systems provide a memory cell and a memory cell system for data serialization. In an embodiment, a half-rate serialization procedure uses a half-rate differential clock to output full-rate serial data. In an embodiment, the memory cell system includes two memory cells each receiving a respective data stream. Each memory cell may be controlled by a respective clock, the clocks being substantially mutually exclusive such that the output of each memory cell becomes alternately tri-stated. Based on the principle of a transistor tri-state or hold mode, if clocks of two memory cells are substantially mutually exclusive, then a tri-stated node can be driven by either of the memory cells in a substantially mutually exclusive manner, effectively multiplexing input parallel data to output serial data. The memory cell system may include a combination of different types of memory cells.
摘要翻译：方法和系统提供用于数据串行化的存储单元和存储单元系统。在一个实施例中，半速率串行化过程使用半速率差分时钟来输出全速率串行数据。在一个实施例中，存储单元系统包括每个接收相应数据流的两个存储单元。每个存储器单元可以由相应的时钟控制，时钟基本相互排斥，使得每个存储器单元的输出变为交替三态。基于晶体管三态或保持模式的原理，如果两个存储单元的时钟基本相互排斥，则三态节点可以以任何一个存储单元以大致相互排斥的方式驱动，有效地复用输入并行数据输出串行数据。存储单元系统可以包括不同类型的存储单元的组合。

8. 发明授权

US09099959B2 Fractional frequency dividing circuit and transmitter 有权
标题翻译：小数分频电路和发射机
公开(公告)号：US09099959B2
公开(公告)日：2015-08-04
申请号：US14167726
申请日：2014-01-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takafumi Yamaji , Tsuneo Suzuki
IPC分类号： H03K23/68 , H03B19/14 , H04B1/04
CPC分类号： H03B19/14 , H03K23/54 , H04B1/04 , H04B2001/0491
摘要： According to one embodiment, there is provided a fractional frequency dividing circuit including an integral frequency dividing circuit and an adjustment circuit. The integral frequency dividing circuit is configured to convert a reference signal to K (K is a positive integer) phase signals. Each of the K phase signals has a frequency of one nth (n is a positive integer) of the reference signal and has different phases from each other. The adjustment circuit is configured to weighting-add a plurality of signals corresponding to the K phase signals and generate a fractional-frequency-divided signal. The fractional-frequency-divided signal has a frequency of m times (m is a positive integer that is not multiplies of n) of each of the plurality of phase signals.
摘要翻译：根据一个实施例，提供了一种包括积分分频电路和调节电路的分数分频电路。积分分频电路被配置为将参考信号转换为K（K是正整数）相位信号。 K个相位信号中的每一个具有参考信号的第n个（n为正整数）的频率，并且具有彼此不同的相位。调整电路被配置为对与K个相位信号相对应的多个信号进行加权加法，并生成分数分频信号。分数分频信号具有多个相位信号中的每一个的m倍的频率（m是不与n相乘的正整数）。

9. 发明授权

US08890726B2 Data interface clock generation 有权
标题翻译：数据接口时钟生成
公开(公告)号：US08890726B2
公开(公告)日：2014-11-18
申请号：US14181969
申请日：2014-02-17
申请人： Intel Corporation
发明人： Wei-Lien Yang
IPC分类号： H03M9/00 , H03K3/017 , H03L7/08 , H04L7/033 , H03K23/68 , H04L1/00 , H03L7/089
CPC分类号： H03K3/017 , H03K23/68 , H03L7/08 , H03L7/0891 , H03M9/00 , H04L1/0003 , H04L7/033
摘要： In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.
摘要翻译：在一个实施例中，装置可以包括时钟发生器以产生第一时钟信号。该装置还可以包括基于传输时钟信号和并行输入数据产生串行数据的串行器。该装置还可以包括基于第一时钟信号和串行数据产生至少两个差分信号的信号发生器。

10. 发明授权

US07336756B2 Reprogrammable bi-directional signal converter 有权
标题翻译：可重复编程的双向信号转换器
公开(公告)号：US07336756B2
公开(公告)日：2008-02-26
申请号：US11258834
申请日：2005-10-25
申请人： Alexander R. Stephens
发明人： Alexander R. Stephens
IPC分类号： H03K23/68 , G06F7/52 , G06G7/16
CPC分类号： G06F7/68 , H03K23/54
摘要： A signal converter is comprised of a plurality of counters (“macro-counters”). In turn, each of the macro-counters is comprised of a plurality of single-bit counters (“micro-counters”) that are adapted to receive configuration data in the form of bit fields. The configuration data is comprised of data corresponding to a plurality of coefficients and of data for grouping the micro-counters into the macro-counters. The coefficients are derived from an input signal/output signal ratio of the converter, and control the manner by which the macro-counters generate the output signal. Thus the converter can be programmed by an end-user in the field.
摘要翻译：信号转换器由多个计数器（“宏计数器”）组成。反过来，每个宏计数器由多个单位计数器（“微计数器”）组成，其适于以位字段的形式接收配置数据。配置数据由对应于多个系数的数据和用于将微计数器分组到宏计数器中的数据组成。系数由转换器的输入信号/输出信号比导出，并控制宏计数器产生输出信号的方式。因此，转换器可以由现场的最终用户编程。

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