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1. 发明申请

US20190243787A1 Memory Systems having Controllers Embedded in Packages of Integrated Circuit Memory 审中-公开
公开(公告)号：US20190243787A1
公开(公告)日：2019-08-08
申请号：US16162905
申请日：2018-10-17
申请人： Micron Technology, Inc.
发明人： Samir Mittal , Gurpreet Anand , Ying Yu Tai , Cheng Yuan Wu
IPC分类号： G06F13/16 , G06F13/42 , G11C16/20 , G06F9/445
CPC分类号： G06F13/1684 , G06F9/445 , G06F13/4234 , G06F13/4247 , G11C16/20
摘要： A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

2. 发明申请

US20180375738A1 SYSTEM AND METHOD ALLOWING FOR DETERMINING RELATIVE POSITIONS OF SLAVE UNITS ALONG A STUB BUS 审中-公开
公开(公告)号：US20180375738A1
公开(公告)日：2018-12-27
申请号：US15935051
申请日：2018-03-25
申请人： NXP B.V.
发明人： Arnoud Pieter van der Wel , Joop Petrus Maria van Lammeren , Luc van Dijk
IPC分类号： H04L12/24 , H04L12/40 , G01R19/10 , G01R19/25
CPC分类号： H04L41/12 , G01R19/10 , G01R19/2513 , G06F13/4247 , G06F2213/0052 , H04L12/40013 , H04L12/40032 , H04L12/40039 , H04L12/40045 , H04L61/2038 , H04L2012/40234 , H04L2012/40273
摘要： The present application relates to a system and a method for determining relative positions slave units along a stub bus with at least a power line and a ground line. Each slave unit is operable in different power modes, which are differentiated by effective resistances between the power and ground lines. A reference voltage potential drop is determined for each slave unit while the slave units are operating in a first power mode. A positioning voltage potential drop is determined for one or more slave units while a selected slave unit is operating in a second power mode. Relative positions of the slave units are determined based on the relative voltage potential drops obtained from the reference and positioning voltage potential drops.

3. 发明申请

US20170351637A1 DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT 有权
公开(公告)号：US20170351637A1
公开(公告)日：2017-12-07
申请号：US15685855
申请日：2017-08-24
申请人： Micron Technology, Inc.
发明人： Doyle Rivers , Paul D. Ruby , Anand S. Ramalingam , Rajesh Sundaram , Julie M. Walker
IPC分类号： G06F13/42 , G06F13/38 , G06F13/14
CPC分类号： G06F13/4247 , G06F13/14 , G06F13/385
摘要： Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

4. 发明授权

US09799302B2 Systems and methods for transmitting video, network, and USB signals over extension media 有权
公开(公告)号：US09799302B2
公开(公告)日：2017-10-24
申请号：US14927336
申请日：2015-10-29
申请人： Icron Technologies Corporation
发明人： Sukhdeep Singh Hundal , Terence Carl Sosniak , David Patrick Frey
IPC分类号： G06F13/14 , G09G5/00 , G06F13/42 , G06F13/38 , G06F13/40
CPC分类号： G09G5/006 , G06F13/385 , G06F13/4081 , G06F13/4247 , G09G2370/10 , G09G2370/12 , G09G2370/14
摘要： In some embodiments, systems, devices, and methods are provided that allow a host device to communicate video information, network information, and USB information over USB via a USB host controller. The video information and the network information are encapsulated within USB and communicated by the USB host controller. In some embodiments, the USB information communicated by the USB host controller is further communicated over a non-USB extension medium by an upstream facing port device and one or more downstream facing port devices.

5. 发明申请

US20170220501A1 COUPLING SYSTEM FOR ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20170220501A1
公开(公告)日：2017-08-03
申请号：US15249484
申请日：2016-08-29
申请人： HONGFUJIN PRECISION ELECTRONICS(CHONGQING)CO. LTD , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： CHING-CHUNG LIN
IPC分类号： G06F13/364 , G06F13/42 , G06F13/40
CPC分类号： G06F13/364 , G06F13/4081 , G06F13/4247 , G06F13/4282
摘要： An electronic device coupling system includes a plurality of electronic devices and an external power supply. The plurality of electronic devices includes a master device and a plurality of slave devices coupleable to the master device one by one. Each electronic device has a sequence number according to an insertion sequence, the sequence number is corresponds to all the information of local electronic device, the sequence numbers of the plurality of electronic devices are sorted according to the insertion sequence, the sequence number of the master device is a first number of the sequence, and the master device is coupleable to at least one slave device by the sequence number and all the information corresponding to the sequence number. The at least one slave device is a customized group of the master device.

6. 发明授权

US09652412B2 Method and apparatus for sending data from multiple sources over a communications bus 有权
公开(公告)号：US09652412B2
公开(公告)日：2017-05-16
申请号：US14456372
申请日：2014-08-11
申请人： Micron Technology, Inc.
发明人： James W. Meyer , Kirsten (Renick) Lunzer
IPC分类号： G06F13/00 , G06F13/16 , G06F13/40 , G06F13/42
CPC分类号： G06F13/161 , G06F13/00 , G06F13/4013 , G06F13/4247 , G06F2213/16
摘要： In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

7. 发明授权

US09626327B2 Memory device for a hierarchical memory architecture 有权
公开(公告)号：US09626327B2
公开(公告)日：2017-04-18
申请号：US14840733
申请日：2015-08-31
申请人： Micron Technology, Inc.
发明人： Sean Eilert , Mark Leinwander
IPC分类号： G06F12/02 , G06F3/06 , G06F13/42 , G11C13/00 , G06F12/08
CPC分类号： G06F13/4247 , G06F3/06 , G06F3/0611 , G06F3/0629 , G06F3/0688 , G06F12/0246 , G06F12/08 , G11C13/0004 , H01L45/06 , Y02D10/13
摘要： In various embodiments, a hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy and/or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. Other embodiments are discussed.

8. 发明授权

US09559389B2 Daisy chain communication bus and protocol 有权
标题翻译：菊花链通信总线和协议
公开(公告)号：US09559389B2
公开(公告)日：2017-01-31
申请号：US13938416
申请日：2013-07-10
申请人： Datang NXP Semiconductors Co., Ltd.
发明人： Pierre De Greef , Matheus Johannus Gerardus Lammers , Johannes Petrus Maria Van Lammeren
IPC分类号： G08C19/22 , H04Q9/00 , H01M14/00 , G01R31/36 , H02J7/04 , H02J7/16 , H01M10/42 , G06F13/42 , B60L11/18
CPC分类号： H01M10/425 , B60L11/1862 , B60L11/1864 , G06F13/4247 , H01M2010/4278 , H01M2220/20 , Y02T10/7005 , Y02T10/7044 , Y02T10/7061 , Y02T90/16
摘要： A battery pack has first and second battery terminals, plural battery cells each with a battery element, a cell supervisor electrically connected to the battery element, and a communication section to communicate with the cell supervisor. The battery elements are connected serially between the first and second battery terminals. Bus interfaces are arranged in alternating fashion with the battery cells to define a daisy chain bus, each such bus interface being configured for signal communication, the interfaces respectively connecting the communication sections of two adjacent battery cells. A battery manager communicates with the battery cells via the daisy chain bus. The battery manager sends a command message to the battery cells using a through mode protocol, and each battery cell sends at least one of a confirmation message and a service request to the battery manager using a shift mode protocol.
摘要翻译：电池组具有第一和第二电池端子，多个电池单元各自具有电池元件，电连接到电池元件的电池主管，以及与电池主管通信的通信部。电池元件串联连接在第一和第二电池端子之间。总线接口与电池单元交替地布置以限定菊花链总线，每个这样的总线接口被配置用于信号通信，所述接口分别连接两个相邻电池单元的通信部分。电池管理器通过菊花链总线与电池单元进行通信。电池管理器使用通过模式协议向电池单元发送命令消息，并且每个电池单元使用移位模式协议向电池管理器发送至少一个确认消息和服务请求。

9. 发明申请

US20160285968A1 LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING 有权
标题翻译：低功耗和低功耗设备与卡特彼勒寻址
公开(公告)号：US20160285968A1
公开(公告)日：2016-09-29
申请号：US15077841
申请日：2016-03-22
申请人： QUALCOMM Incorporated
发明人： Lalan Jee Mishra , James Panian , Richard Wietfeldt
IPC分类号： H04L29/08 , H04L29/12
CPC分类号： H04L67/1091 , G06F13/4247 , G06F2213/0052 , H04L61/2007 , H04L61/604
摘要： An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.
摘要翻译：提供了一种枚举技术，其不需要将通过P2P链接连接到主机设备的从设备的地址预先分配。关于设备之间的任何P2P链路，一个设备具有主接口，其余设备具有从接口。为了区分主从接口，可以使用主/从状态位。每个P2P链路具有可以与相应接口（从属或主机）的状态位连接以形成节点ID的链路ID。主设备从每个从设备接收代表从设备的节点ID的级联和从设备与主设备之间的任何介入接口的节点ID的唯一的级联地址。然后，主机设备为每个从设备分配唯一的笛卡尔地址。

10. 发明申请

US20160224265A1 MEMORY POWER MANAGEMENT AND DATA CONSOLIDATION 有权
公开(公告)号：US20160224265A1
公开(公告)日：2016-08-04
申请号：US15138694
申请日：2016-04-26
申请人： International Business Machines Corporation
发明人： Diyanesh B. Chinnakkonda Vidyapoornachary , Edgar R. Cordero , Anand Haridass , Arun Joseph
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0625 , G06F1/3275 , G06F1/3293 , G06F3/0647 , G06F3/0656 , G06F3/0658 , G06F3/0673 , G06F12/0893 , G06F13/28 , G06F13/4247 , G06F2212/1028 , G06F2212/151 , Y02D10/14 , Y02D10/151
摘要： According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.

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