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1. 发明申请

US20140089647A1 Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch 有权
标题翻译：广泛问题的分支预测器，任意对齐获取
公开(公告)号：US20140089647A1
公开(公告)日：2014-03-27
申请号：US13625382
申请日：2012-09-24
申请人： Ian D. Kountanis , Gerard R. Williams, III , James B. Keller
发明人： Ian D. Kountanis , Gerard R. Williams, III , James B. Keller
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3005 , G06F9/30058 , G06F9/38 , G06F9/3844 , G06F9/3848
摘要： In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch.
摘要翻译：在一个实施例中，处理器可以被配置为从指令高速缓存（“取出组”）获取N个指令字节，即使获取组跨越高速缓存行边界。分支预测器可以被配置为在获取组中产生多达M个分支的分支预测，其中M是可以包括在获取组中的最大分支数。在一个实施例中，分支方向预测器可以响应于错误预测而被更新，并且还响应于在预测之间的转换阈值内的分支预测。为了避免查找以确定是否要执行阈值更新，分支预测器可以在预测期间检测阈值更新，并且可以用分支发送指示。

2. 发明授权

US08493863B2 Hierarchical fabric control circuits 有权
标题翻译：分层结构控制电路
公开(公告)号：US08493863B2
公开(公告)日：2013-07-23
申请号：US13008184
申请日：2011-01-18
申请人： Gurjeet S. Saund , James B. Keller , Michael Frank
发明人： Gurjeet S. Saund , James B. Keller , Michael Frank
IPC分类号： H04L12/26
CPC分类号： H04L49/503 , H04L49/205
摘要： In an embodiment, one or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, in some embodiments. In other embodiments that include a hierarchical communication fabric, fabric control circuits may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.
摘要翻译：在一个实施例中，可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。在一些实施例中，结构控制电路可以包括在组件的接口上到通信结构。在包括分层通信结构的其他实施例中，结构控制电路可以可选地或另外包括。织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

3. 发明授权

US08255670B2 Replay reduction for power saving 有权
标题翻译：节电减重
公开(公告)号：US08255670B2
公开(公告)日：2012-08-28
申请号：US12619751
申请日：2009-11-17
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译：在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。

4. 发明授权

US08078772B2 Digital phase relationship lock loop 有权
公开(公告)号：US08078772B2
公开(公告)日：2011-12-13
申请号：US12908605
申请日：2010-10-20
申请人： James Wang , Zongjian Chen , James B. Keller
发明人： James Wang , Zongjian Chen , James B. Keller
IPC分类号： G06F13/00 , H03K5/135
CPC分类号： G06F5/14
摘要： In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

5. 发明授权

US07752474B2 L1 cache flush when processor is entering low power mode 有权
标题翻译：当处理器进入低功耗模式时，L1缓存刷新
公开(公告)号：US07752474B2
公开(公告)日：2010-07-06
申请号：US11525584
申请日：2006-09-22
申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
发明人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
摘要翻译：在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。

6. 发明授权

US07752366B2 Non-blocking address switch with shallow per agent queues 有权
标题翻译：非阻塞地址切换，每个代理队列较浅
公开(公告)号：US07752366B2
公开(公告)日：2010-07-06
申请号：US12263255
申请日：2008-10-31
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

7. 发明申请

US20080077813A1 Fast L1 flush mechanism 有权
标题翻译：快速L1冲洗机构
公开(公告)号：US20080077813A1
公开(公告)日：2008-03-27
申请号：US11525584
申请日：2006-09-22
申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campell
发明人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campell
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
摘要翻译：在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。

8. 发明授权

US07124286B2 Establishing an operating mode in a processor 有权
标题翻译：在处理器中建立操作模式
公开(公告)号：US07124286B2
公开(公告)日：2006-10-17
申请号：US09824890
申请日：2001-04-02
申请人： Kevin J. McGrath , Michael T. Clark , James B. Keller
发明人： Kevin J. McGrath , Michael T. Clark , James B. Keller
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30036 , G06F9/30101 , G06F9/30112 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30174 , G06F9/30189 , G06F9/342 , G06F9/45516
摘要： A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state).
摘要翻译：处理器支持地址大小大于32位的处理模式，操作数大小可以是32位或64位。地址大小可以名义上表示为64位，尽管在处理模式下，处理器的各种实施例可以实现超过32位，高达并包括64位的任何地址大小。可以通过将控制寄存器中的使能指示置于使能状态并且通过将段描述符中的第一操作模式指示和第二操作模式指示设置为预定状态来建立处理模式。可以使用第一操作模式指示和第二操作模式指示的其他组合来提供与x86处理器架构兼容的32位和16位处理的兼容性模式（使能指示保持在使能状态）。

9. 发明授权

US06928500B1 High speed bus system that incorporates uni-directional point-to-point buses 失效
标题翻译：采用单向点对点总线的高速总线系统
公开(公告)号：US06928500B1
公开(公告)日：2005-08-09
申请号：US08883118
申请日：1997-06-26
申请人： Raj Ramanujan , James B. Keller , William A. Samaras , John Derosa , Robert E. Stewart
发明人： Raj Ramanujan , James B. Keller , William A. Samaras , John Derosa , Robert E. Stewart
IPC分类号： G06F15/167 , G06F15/173 , H04L12/28 , H04L12/403 , G06F13/14 , G06F13/36
CPC分类号： H04L12/403 , G06F15/167 , G06F15/173 , H04L12/4625
摘要： A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.
摘要翻译：一种用于共享存储器系统的高速总线系统，其允许多个处理器与多处理器共享存储器系统的存储器阵列之间的命令和数据的高速传输，其中高速总线系统包括中央单元和连接在多个处理器和共享存储器之间的一系列单向总线，中央单元包括仲裁逻辑和一系列多路复用器，以确定哪些CPU被授权访问共享总线，调度逻辑与仲裁逻辑和多路复用器，以确定哪些CPU被授权访问共享总线，以及端口逻辑，用于组合CPU传输并确定这些传输是否有效。

10. 发明授权

US06888843B2 Response virtual channel for handling all responses 失效
标题翻译：响应虚拟通道来处理所有响应
公开(公告)号：US06888843B2
公开(公告)日：2005-05-03
申请号：US09398624
申请日：1999-09-17
申请人： James B. Keller , Derrick R. Meyer
发明人： James B. Keller , Derrick R. Meyer
IPC分类号： G06F13/40 , H04L12/54
CPC分类号： G06F13/405
摘要： A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical/protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, nodes within the computer system may be configured to preallocate resources to process response packets. Some response packets may have logical conflicts with other response packets, and hence would normally not be allocable to the same virtual channel. However, by preallocating response-processing resources, response packets are accepted by the destination node. Thus, any resource conflicts which may occur are temporary (as the response packets which make forward progress are processable). Viewed in another way, response packets may be logically independent if the destination node is capable of processing the response packets upon receipt. Accordingly, a response virtual channel is formed to which each response packet belongs.
摘要翻译：计算机系统采用虚拟通道并为虚拟通道分配不同的资源。没有逻辑/协议相关冲突的数据包被分组成虚拟通道。因此，在分离的虚拟通道中的分组之间发生逻辑冲突。虚拟通道内的数据包可能共享资源（从而遇到资源冲突），但不同虚拟通道内的数据包可能不共享资源。由于可能遇到资源冲突的数据包不会出现逻辑冲突，并且由于可能遇到逻辑冲突的数据包不会遇到资源冲突，因此可能会实现无死锁操作。此外，计算机系统内的节点可以被配置为预先分配资源以处理响应分组。一些响应分组可能与其他响应分组具有逻辑冲突，因此通常不能分配给相同的虚拟信道。然而，通过预分配响应处理资源，响应分组被目的节点接受。因此，可能发生的任何资源冲突都是临时的（因为可以进行进展的响应数据包是可处理的）。以另一种方式观察，如果目的地节点在接收时能够处理响应分组，则响应分组可以在逻辑上是独立的。因此，形成每个响应分组所属的响应虚拟信道。

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