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1. 发明授权

US6064743A Wavetable audio synthesizer with waveform volume control for eliminating zipper noise 失效
公开(公告)号：US6064743A
公开(公告)日：2000-05-16
申请号：US863887
申请日：1997-05-28
申请人： David N. Suggs
发明人： David N. Suggs
IPC分类号： G06F7/02 , G10H7/02 , H03K23/68 , H03G3/00
CPC分类号： G10H7/02 , G06F7/026 , H03K23/68 , G10H2210/201 , G10H2250/115 , G10H2250/545 , G10H2250/605 , G10H2250/621
摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects processing, the data can be provided with left and right offset volume components which determine how much of the effect is heard and its stereo position. The data is then stored in the left and right accumulators.

2. 发明授权

US5546039A Charge dissipation in capacitively loaded ports 失效
标题翻译：电容负载端口的电荷消耗
公开(公告)号：US5546039A
公开(公告)日：1996-08-13
申请号：US423059
申请日：1995-04-17
申请人： Larry D. Hewitt , Ryan Feemster
发明人： Larry D. Hewitt , Ryan Feemster
IPC分类号： G06F3/16 , G06F7/02 , G06F9/38 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K23/68 , H03M3/02 , H03M7/32 , H03K17/16 , H03K5/12
CPC分类号： G06F3/16 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , H03K23/68 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.
摘要翻译：触发电路的级联顺序地激活一系列平行的下拉路径，该反向响应反应于指示电容负载端口上的电位与可选阈值电压之间的对应关系的下拉信号。触发电路用公共信号计时，从而在随后的触发级之前顺序地传播下拉信号以顺序激活相应的并行路径。在优选实施例中，顺序级联的D触发器控制多个下拉路径，以调节单片音频个人计算机IC游戏端口上的操纵杆电容负载的充电和放电。为了启动操纵杆电容器的充电，触发器响应于系统写信号同时禁用下拉路径。为了放电操纵杆电容器，触发器顺序地传播比较器导出的下拉信号，以顺序使得下拉路径可控制地耗散累积的电荷。

3. 发明授权

US5534844A Comparator circuit 失效
标题翻译：比较器电路
公开(公告)号：US5534844A
公开(公告)日：1996-07-09
申请号：US415266
申请日：1995-04-03
申请人： David Norris
发明人： David Norris
IPC分类号： G06F7/02 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03K23/70
CPC分类号： G06F7/026 , H03K23/68 , H03K23/70 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/115 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A static-type comparator, which compares the magnitude of a first binary number with a second binary number and determines if the first binary number is equal to, greater than, or less than the second binary number, is described. The comparator comprises a carry chain of comparison cells. Each comparison cell in the carry chain compares the magnitude of a different bit position of the first number with a corresponding bit position in the second number. The comparison cells input a first voltage signal, representing a binary value of a bit position of the first number, and a second voltage signal, representing a binary value of a corresponding bit position of the second number. A voltage signal from a voltage source Vcc is input into the carry chain and propagates through the chain until a comparison cell detects that there is a difference in magnitudes for a particular bit position. If a difference in magnitudes is detected, the comparison cell will output a voltage signal indicating whether the first number is greater than or less than the second number. If the numbers are equal, voltage signal Vcc propagates through the entire carry chain and is output. In the preferred embodiment, the comparator includes decode circuitry for decoding the carry chain's outputs. The comparator preferably also inputs a timing signal to time the comparator's operations.
摘要翻译：静态型比较器，其将第一二进制数的大小与第二二进制数进行比较，并确定第一二进制数是否等于，大于或小于第二二进制数。比较器包括比较单元的进位链。进位链中的每个比较单元将第一数字的不同位位置的大小与第二数目中的对应位位置进行比较。比较单元输入表示第一数字的位位置的二进制值的第一电压信号和表示第二数字的对应位位置的二进制值的第二电压信号。来自电压源Vcc的电压信号被输入到进位链中并且通过链传播，直到比较单元检测到特定位位置的幅度差异为止。如果检测到大小差异，则比较单元将输出指示第一数字是大于还是小于第二数字的电压信号。如果数字相等，则电压信号Vcc通过整个进位链传播并被输出。在优选实施例中，比较器包括用于对进位链的输出进行解码的解码电路。比较器优选地还输入定时信号以对比较器的操作进行计时。

4. 发明授权

US6058066A Enhanced register array accessible by both a system microprocessor and a wavetable audio synthesizer 有权
标题翻译：增强的寄存器阵列可由系统微处理器和波形音频合成器访问
公开(公告)号：US6058066A
公开(公告)日：2000-05-02
申请号：US160992
申请日：1998-09-25
申请人： David E. Norris , Larry D. Hewitt , Jeffrey M. Blumenthal
发明人： David E. Norris , Larry D. Hewitt , Jeffrey M. Blumenthal
IPC分类号： G06F3/16 , G06F7/02 , G06F9/38 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K23/68 , H03M3/02 , H03M7/32 , G11C8/00
CPC分类号： H03K23/68 , G06F3/162 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.
摘要翻译：一种可由PC音频电路的系统微处理器和数字信号处理器访问的寄存器阵列，包括：（i）具有连接到数字信号处理器输入/输出端口的第一端口的随机存取存储器（RAM），以及第二端口连接到RAM输入/输出端口; （ii）连接到RAM输入/输出端口并具有到寄存器数据总线的连接的寄存器数据端口; （iii）用于定时寄存器阵列操作的定时电路; （iv）用于分别在所述RAM中选择行和列的行和列选择电路; 和（v）连接到所述定时电路的输入/输出通道就绪信号线。 RAM包括多个边沿位，每个边沿位存储指示存储在所述RAM中的一行数据值的处理是处于活动还是非活动状态的值。当RAM不空闲或微处理器寻求访问当前受数字信号处理器访问的RAM的一行时，系统微处理器被禁止访问RAM。如果微处理器禁止向RAM写入数据，则数据可能会临时存储在寄存器数据端口中，直到微处理器的访问被使能为止。

5. 发明授权

US5794021A Variable frequency clock generation circuit using aperiodic patterns 失效
标题翻译：可变频时钟发生电路采用非周期性模式
公开(公告)号：US5794021A
公开(公告)日：1998-08-11
申请号：US483619
申请日：1995-06-07
申请人： Larry D. Hewitt
发明人： Larry D. Hewitt
IPC分类号： G06F3/16 , G06F7/02 , G06F9/38 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K23/68 , H03M3/02 , H03M7/32 , G06F1/08
CPC分类号： G06F3/16 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , H03K23/68 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A method and circuit for generating a selectively variable clock signal from one of 256 frequencies within a specified range from two fixed frequency oscillator source signals is provided. The method and circuitry maintain a substantially fifty-percent duty cycle in the output clock signal.
摘要翻译：提供一种用于从两个固定频率振荡器源信号的指定范围内的256个频率之一产生选择性可变时钟信号的方法和电路。该方法和电路在输出时钟信号中保持大致百分之五十的占空比。

6. 发明授权

US5742695A Wavetable audio synthesizer with waveform volume control for eliminating zipper noise 失效
标题翻译：波形音频合成器，具有消除拉链噪音的波形音量控制
公开(公告)号：US5742695A
公开(公告)日：1998-04-21
申请号：US333562
申请日：1994-11-02
申请人： David N. Suggs
发明人： David N. Suggs
IPC分类号： G06F7/02 , G10H7/02 , H03K23/68 , H03G3/00
CPC分类号： G10H7/02 , G06F7/026 , H03K23/68 , G10H2210/201 , G10H2250/115 , G10H2250/545 , G10H2250/605 , G10H2250/621
摘要： A wavetable audio synthesizer with means for eliminating zipper noise caused by large volume increments, especially at slower rates of volume increment. The wavetable audio synthesizer includes shift circuitry which stores the value of volume increment in binary format and shifts the value right when the shift circuitry is enabled. Shifting the increment value right divides the value by an amount based on the number of bit positions shifted. For example, in the preferred embodiment, the volume increment value is shifted right three positions, thereby dividing it by three and effectively reducing the increment value. When the synthesizer is programmed to increment the volume at a slow rate, preferably the shift circuitry is automatically enabled. Those volume increment bits which are shifted right may be added to the current value of the volume to provide more resolution to this value.
摘要翻译：一种波形音频合成器，具有消除大体积增量引起的拉链噪声的方法，特别是在较慢的音量增量速率下。波动音频合成器包括移位电路，其存储二进制格式的音量增量值，并且当移位电路被使能时将该值向右移位。移动增量值右移将基于移位的位位数的数值分开。例如，在优选实施例中，体积增量值向右移位三个位置，从而将其除以3并有效地减小增量值。当合成器被编程为以慢速率增加音量时，优选地，移位电路被自动启用。向右移动的那些音量增量位可以被添加到音量的当前值，以便为该值提供更多的分辨率。

7. 发明授权

US6047073A Digital wavetable audio synthesizer with delay-based effects processing 失效
公开(公告)号：US6047073A
公开(公告)日：2000-04-04
申请号：US334462
申请日：1994-11-02
申请人： David Norris , David N. Suggs
发明人： David Norris , David N. Suggs
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03G3/00
CPC分类号： G10H1/0066 , G06F3/162 , G10H1/125 , G10H7/002 , H03K23/68 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/605 , G10H2250/611
摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects processing, the data can be provided with left and right offset volume components which determine how much of the effect is heard and its stereo position. The data is then stored in the left and right accumulators.

8. 发明授权

US5890017A Application-independent audio stream mixer 失效
标题翻译：独立于音频流的混音器
公开(公告)号：US5890017A
公开(公告)日：1999-03-30
申请号：US753084
申请日：1996-11-20
申请人： Michael C. Tulkoff , Ravinder P. Wadehra
发明人： Michael C. Tulkoff , Ravinder P. Wadehra
IPC分类号： G06F3/16 , G10H1/00 , G10H7/00 , G06F13/00
CPC分类号： G10H7/006 , G06F3/16 , G10H1/0058 , G10H2240/031 , G10H2240/056 , G10H2240/071 , G10H2250/605
摘要： Method and system aspects output a single audio stream from a plurality of audio streams provided by at least one application program running on a computer system with an audio device. Production of the single audio stream includes forming a server process in the computer system, emulating the audio device with the server process to allow any combination of audio stream formats, and manipulating the plurality of audio streams with the server process to form the single audio stream for maintaining transparency to the at least one application program.
摘要翻译：方法和系统方面从由具有音频设备的计算机系统上运行的至少一个应用程序提供的多个音频流输出单个音频流。单个音频流的制作包括在计算机系统中形成服务器进程，利用服务器进程模拟音频设备，以允许音频流格式的任何组合，并且通过服务器进程操纵多个音频流以形成单个音频流以保持至少一个应用程序的透明度。

9. 发明授权

US5860065A Apparatus and method for automatically providing background music for a card message recording system 失效
标题翻译：用于自动提供卡片消息记录系统的背景音乐的装置和方法
公开(公告)号：US5860065A
公开(公告)日：1999-01-12
申请号：US731727
申请日：1996-10-21
申请人： Jerry Hsu
发明人： Jerry Hsu
IPC分类号： G10H1/26 , G10H1/36 , G10L15/26 , G10L3/02 , G10L5/02 , G10L9/00
CPC分类号： G10H1/26 , G10H1/361 , G10L15/26 , G10H2250/595 , G10H2250/605
摘要： The invention relates to a method and an apparatus for automatically providing background music for a card message recording system thereby to enhance the feature of a conventional card recording system. The invention mainly comprises a speech analyzer, a memory, a speech synthesizer, a melody generator, a mixer and a speaker. At recording mode, the message is processed in speech analyzer and then stored in the memory. At playing mode, the message is read and processed in speech synthesizer. Then the mixer reads the message and the background music at proper time intervals such that when the volume of the message is increased, the volume of the musical signals fades and vice versa. Consequently, the mixed signals are played out by the speaker.
摘要翻译：本发明涉及一种用于自动提供卡片消息记录系统的背景音乐的方法和装置，从而增强传统卡片记录系统的特征。本发明主要包括语音分析器，存储器，语音合成器，旋律发生器，混音器和扬声器。在录音模式下，该消息在语音分析仪中处理，然后存储在存储器中。在播放模式下，在语音合成器中读取和处理消息。然后，混音器以适当的时间间隔读取消息和背景音乐，使得当消息的音量增加时，音乐信号的音量消失，反之亦然。因此，混合信号由扬声器播放。

10. 发明授权

US5859995A Method and apparatus for coordinating combinatorial logic-clocked state machines 失效
标题翻译：用于协调组合逻辑时钟状态机的方法和装置
公开(公告)号：US5859995A
公开(公告)日：1999-01-12
申请号：US373689
申请日：1995-01-17
申请人： Larry D. Hewitt
发明人： Larry D. Hewitt
IPC分类号： H03K19/003 , G06F3/16 , G06F7/02 , G06F9/38 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K3/02 , H03K23/68 , H03M3/02 , H03M7/32 , G06F1/04
CPC分类号： G06F3/16 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , H03K23/68 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the upstream SM output state and selected data at the triggering circuit input. The triggering circuit and the upstream SM are clocked from a common signal preventing the upstream SM from changing state before the triggering circuit produces the proper signal to impose the expected state on the downstream SM. The downstream SM takes on the correct output state in dependable correspondence with a selected upstream SM output state. In a preferred embodiment, a D flip-flop generates a triggering signal in response to a selected combination of upstream SM output state and system data. The D flip-flop triggering signal imposes a selected output state on a downstream SM through the asynchronous SET and CLEAR inputs of the downstream SM flip-flops. Because the D flip-flop and upstream SM are both clocked off the same trailing edge of the WRITE line, the upstream SM and D flip-flop change state together, preventing the upstream SM from changing state before the triggering signal is generated.
摘要翻译：触发电路消除上游和下游状态机（“SM”）的差分组合逻辑时钟的传播差异。触发电路响应于在触发电路输入处出现上游SM输出状态和所选择的数据的适当组合，在下游SM上施加输出状态。触发电路和上游SM从公共信号计时，防止上游SM在触发电路产生适当信号之前改变状态，以将预期状态施加在下游SM上。下游SM与选择的上游SM输出状态可靠地对应地进行正确的输出状态。在优选实施例中，D触发器响应于所选择的上游SM输出状态和系统数据的组合而产生触发信号。 D触发器触发信号通过下游SM触发器的异步SET和CLEAR输入在下游SM上施加选择的输出状态。因为D触发器和上游SM都被写入WRITE线的相同后沿，所以上行SM和D触发器一起改变状态，从而防止上游SM在产生触发信号之前改变状态。

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