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1. 发明授权

US5917917A Reduced-memory reverberation simulator in a sound synthesizer 失效
标题翻译：声音合成器中的减速记忆混响模拟器
公开(公告)号：US5917917A
公开(公告)日：1999-06-29
申请号：US713343
申请日：1996-09-13
申请人： Michael V. Jenkins , Qiujie Dong , Edward M. Veeser
发明人： Michael V. Jenkins , Qiujie Dong , Edward M. Veeser
IPC分类号： G10H1/00 , G10K15/12 , H03G3/00
CPC分类号： G10H1/0091 , G10K15/12 , G10H2210/201 , G10H2210/281 , G10H2240/056 , G10H2250/121 , G10H2250/611
摘要： A sound or music synthesizer includes a reverberation simulator having a substantially reduced volatile storage, random access memory, or buffer size in comparison to conventional reverberation simulators by decimating the sound signal prior to applying the sound signal to a reverberator and then interpolating the sound signal generated by the reverberator to restore the sample frequency. The substantial reduction in buffer size enables the usage of the reverberator in low-cost, reduced size and single-chip environments.
摘要翻译：声音或音乐合成器包括与常规混响模拟器相比具有显着降低的易失性存储器，随机存取存储器或缓冲器大小的混响仿真器，通过在将声音信号施加到混响器之前抽取声音信号，然后内插产生的声音信号由混响器恢复采样频率。缓冲区大小的实质减少使得可以以低成本，减小尺寸和单芯片环境使用混响器。

2. 发明授权

US5648778A Stereo audio CODEC 失效
标题翻译：立体声音频编解码器
公开(公告)号：US5648778A
公开(公告)日：1997-07-15
申请号：US683754
申请日：1996-07-17
申请人： Alfredo R. Linz , Carlin Dru Cabler , Glen W. Brown , Martin P. Soques
发明人： Alfredo R. Linz , Carlin Dru Cabler , Glen W. Brown , Martin P. Soques
IPC分类号： F02B75/02 , G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03M7/32 , H03M1/00
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0058 , G10H1/0066 , G10H1/125 , G10H7/002 , F02B2075/027 , G10H2230/035 , G10H2240/311 , G10H2250/115 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.
摘要翻译：立体声音频CODEC，包括用于执行D / A和A / D转换的装置，用于在衰减/增益变化期间减少数字感应噪声的装置，数据格式转换装置，模拟和数字滤波装置，模拟混合装置，片上16- 采样，32位宽记录和播放FIFO，与外部串行DSP的串行接口，用于补充片上记录和播放FIFO，控制寄存器，寄存器数据总线和合成器DAC的大型本地存储器。

3. 发明授权

US5581253A Implementation and method for a digital sigma-delta modulator 失效
标题翻译：数字Σ-Δ调制器的实现和方法
公开(公告)号：US5581253A
公开(公告)日：1996-12-03
申请号：US510139
申请日：1995-08-03
申请人： Glen W. Brown
发明人： Glen W. Brown
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03M7/32 , H03M3/00
CPC分类号： H03M7/3035 , G06F3/16 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611 , H03M7/3028
摘要： Described herein is a digital sigma-delta modulator and method for converting a multi-bit digital input signal to a 1-bit digital output signal. The digital sigma-delta modulator performs a noise shaping filter function for a digital-to-analog circuit. A series of cascaded integration stages are implemented with a plurality of multiplexed adders which perform the integration functions.
摘要翻译：这里描述的是用于将多位数字输入信号转换为1位数字输出信号的数字Σ-Δ调制器和方法。数字Σ-Δ调制器为数模转换电路执行噪声整形滤波功能。一系列级联的集成阶段通过执行集成功能的多个多路复用加法器实现。

4. 发明授权

US5546039A Charge dissipation in capacitively loaded ports 失效
标题翻译：电容负载端口的电荷消耗
公开(公告)号：US5546039A
公开(公告)日：1996-08-13
申请号：US423059
申请日：1995-04-17
申请人： Larry D. Hewitt , Ryan Feemster
发明人： Larry D. Hewitt , Ryan Feemster
IPC分类号： G06F3/16 , G06F7/02 , G06F9/38 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K23/68 , H03M3/02 , H03M7/32 , H03K17/16 , H03K5/12
CPC分类号： G06F3/16 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , H03K23/68 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.
摘要翻译：触发电路的级联顺序地激活一系列平行的下拉路径，该反向响应反应于指示电容负载端口上的电位与可选阈值电压之间的对应关系的下拉信号。触发电路用公共信号计时，从而在随后的触发级之前顺序地传播下拉信号以顺序激活相应的并行路径。在优选实施例中，顺序级联的D触发器控制多个下拉路径，以调节单片音频个人计算机IC游戏端口上的操纵杆电容负载的充电和放电。为了启动操纵杆电容器的充电，触发器响应于系统写信号同时禁用下拉路径。为了放电操纵杆电容器，触发器顺序地传播比较器导出的下拉信号，以顺序使得下拉路径可控制地耗散累积的电荷。

5. 发明授权

US5534844A Comparator circuit 失效
标题翻译：比较器电路
公开(公告)号：US5534844A
公开(公告)日：1996-07-09
申请号：US415266
申请日：1995-04-03
申请人： David Norris
发明人： David Norris
IPC分类号： G06F7/02 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03K23/70
CPC分类号： G06F7/026 , H03K23/68 , H03K23/70 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/115 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A static-type comparator, which compares the magnitude of a first binary number with a second binary number and determines if the first binary number is equal to, greater than, or less than the second binary number, is described. The comparator comprises a carry chain of comparison cells. Each comparison cell in the carry chain compares the magnitude of a different bit position of the first number with a corresponding bit position in the second number. The comparison cells input a first voltage signal, representing a binary value of a bit position of the first number, and a second voltage signal, representing a binary value of a corresponding bit position of the second number. A voltage signal from a voltage source Vcc is input into the carry chain and propagates through the chain until a comparison cell detects that there is a difference in magnitudes for a particular bit position. If a difference in magnitudes is detected, the comparison cell will output a voltage signal indicating whether the first number is greater than or less than the second number. If the numbers are equal, voltage signal Vcc propagates through the entire carry chain and is output. In the preferred embodiment, the comparator includes decode circuitry for decoding the carry chain's outputs. The comparator preferably also inputs a timing signal to time the comparator's operations.
摘要翻译：静态型比较器，其将第一二进制数的大小与第二二进制数进行比较，并确定第一二进制数是否等于，大于或小于第二二进制数。比较器包括比较单元的进位链。进位链中的每个比较单元将第一数字的不同位位置的大小与第二数目中的对应位位置进行比较。比较单元输入表示第一数字的位位置的二进制值的第一电压信号和表示第二数字的对应位位置的二进制值的第二电压信号。来自电压源Vcc的电压信号被输入到进位链中并且通过链传播，直到比较单元检测到特定位位置的幅度差异为止。如果检测到大小差异，则比较单元将输出指示第一数字是大于还是小于第二数字的电压信号。如果数字相等，则电压信号Vcc通过整个进位链传播并被输出。在优选实施例中，比较器包括用于对进位链的输出进行解码的解码电路。比较器优选地还输入定时信号以对比较器的操作进行计时。

6. 发明授权

US6047073A Digital wavetable audio synthesizer with delay-based effects processing 失效
公开(公告)号：US6047073A
公开(公告)日：2000-04-04
申请号：US334462
申请日：1994-11-02
申请人： David Norris , David N. Suggs
发明人： David Norris , David N. Suggs
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03G3/00
CPC分类号： G10H1/0066 , G06F3/162 , G10H1/125 , G10H7/002 , H03K23/68 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/605 , G10H2250/611
摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects processing, the data can be provided with left and right offset volume components which determine how much of the effect is heard and its stereo position. The data is then stored in the left and right accumulators.

7. 发明授权

US6005505A Fourth order digital noise shaper circuit 失效
标题翻译：四阶数字噪声整形电路
公开(公告)号：US6005505A
公开(公告)日：1999-12-21
申请号：US668532
申请日：1996-06-20
申请人： Alfredo Linz
发明人： Alfredo Linz
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03M7/32 , H03M3/00
CPC分类号： H03M7/3035 , G06F3/16 , G10H1/0066 , G10H1/125 , G10H7/002 , H03K23/68 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611 , H03M7/3028
摘要： A digital noise shaper circuit is provided which includes a signal transfer function and a noise transfer function, with associated coefficients and gain scaling factors, which ensures a predetermined frequency response, signal passband and noise stopband, and which converts a multi-bit digital signal to a 1-bit digital signal.
摘要翻译：提供一种数字噪声整形器电路，其包括信号传递函数和噪声传递函数，具有相关联的系数和增益缩放因子，其确保预定的频率响应，信号通带和噪声阻挡带，并将多位数字信号转换为 1位数字信号。

8. 发明授权

US5859995A Method and apparatus for coordinating combinatorial logic-clocked state machines 失效
标题翻译：用于协调组合逻辑时钟状态机的方法和装置
公开(公告)号：US5859995A
公开(公告)日：1999-01-12
申请号：US373689
申请日：1995-01-17
申请人： Larry D. Hewitt
发明人： Larry D. Hewitt
IPC分类号： H03K19/003 , G06F3/16 , G06F7/02 , G06F9/38 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K3/02 , H03K23/68 , H03M3/02 , H03M7/32 , G06F1/04
CPC分类号： G06F3/16 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , H03K23/68 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the upstream SM output state and selected data at the triggering circuit input. The triggering circuit and the upstream SM are clocked from a common signal preventing the upstream SM from changing state before the triggering circuit produces the proper signal to impose the expected state on the downstream SM. The downstream SM takes on the correct output state in dependable correspondence with a selected upstream SM output state. In a preferred embodiment, a D flip-flop generates a triggering signal in response to a selected combination of upstream SM output state and system data. The D flip-flop triggering signal imposes a selected output state on a downstream SM through the asynchronous SET and CLEAR inputs of the downstream SM flip-flops. Because the D flip-flop and upstream SM are both clocked off the same trailing edge of the WRITE line, the upstream SM and D flip-flop change state together, preventing the upstream SM from changing state before the triggering signal is generated.
摘要翻译：触发电路消除上游和下游状态机（“SM”）的差分组合逻辑时钟的传播差异。触发电路响应于在触发电路输入处出现上游SM输出状态和所选择的数据的适当组合，在下游SM上施加输出状态。触发电路和上游SM从公共信号计时，防止上游SM在触发电路产生适当信号之前改变状态，以将预期状态施加在下游SM上。下游SM与选择的上游SM输出状态可靠地对应地进行正确的输出状态。在优选实施例中，D触发器响应于所选择的上游SM输出状态和系统数据的组合而产生触发信号。 D触发器触发信号通过下游SM触发器的异步SET和CLEAR输入在下游SM上施加选择的输出状态。因为D触发器和上游SM都被写入WRITE线的相同后沿，所以上行SM和D触发器一起改变状态，从而防止上游SM在产生触发信号之前改变状态。

9. 发明授权

US5598158A Digital noise shaper circuit 失效
标题翻译：数字噪声整形电路
公开(公告)号：US5598158A
公开(公告)日：1997-01-28
申请号：US333386
申请日：1994-11-02
申请人： Alfredo R. Linz
发明人： Alfredo R. Linz
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03M7/32 , H03M3/02
CPC分类号： H03M7/3035 , G06F3/16 , G10H1/0066 , G10H1/125 , G10H7/002 , H03K23/68 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611 , H03M7/3028
摘要： A digital noise shaper circuit is provided which includes a signal transfer function and a noise transfer function, with associated coefficients and gain scaling factors, which ensures a predetermined frequency response, signal passband and noise stopband, and which converts a multi-bit digital signal to a 1-bit digital signal.
摘要翻译：提供一种数字噪声整形器电路，其包括信号传递函数和噪声传递函数，具有相关联的系数和增益缩放因子，其确保预定的频率响应，信号通带和噪声阻挡带，并将多位数字信号转换为 1位数字信号。

10. 发明授权

US6137046A Tone generator device using waveform data memory provided separately therefrom 失效
标题翻译：使用与其分开提供的波形数据存储器的音调发生器装置
公开(公告)号：US6137046A
公开(公告)日：2000-10-24
申请号：US121083
申请日：1998-07-23
申请人： Ryo Kamiya
发明人： Ryo Kamiya
IPC分类号： G10H7/02 , G10H7/00
CPC分类号： G10H7/02 , G10H2240/275 , G10H2250/121 , G10H2250/611 , G10H2250/621
摘要： Tone generator device, which is applied to a computer, has no waveform memory of its own and is connected via an extended bus to the computer having a main memory where waveform sample data are prestored. When a tone of predetermined pitch is to be reproduced, the tone generator device designates a block of a specific quantity of the waveform sample data in accordance with the pitch to be reproduced and requests that the block be read out from the main memory and burst-transmitted via the extended bus. The burst-transmitted waveform sample data are temporarily stored in an input buffer and then read out from the buffer in accordance with pitch information to generate tone waveform data of the desired pitch. The burst transmission of the data block and subsequent tone waveform data generation are carried out at high speed asynchronously with a predetermined reproduction sampling cycle. The generated tone waveform data are output via an output data in the predetermined reproduction sampling cycle. To raise the upper limit on the reproducible pitch without a need to increase the capacity of the input buffer, a thinned version of the original waveform sample data may also be prestored in the main memory so that the thinned waveform sample data can be selected to permit the raised upper limit. Alternatively, such thinned waveform sample data may be generated by thinning the original waveform sample data, rather than being prestored in the main memory.
摘要翻译：应用于计算机的音频发生器装置没有自己的波形存储器，并且通过扩展总线连接到具有预存有波形样本数据的主存储器的计算机。当要再现预定音调的音调时，乐音发生器装置根据要再现的音调指定一个特定数量的波形采样数据的块，并请求从主存储器读出该块，通过扩展总线传输。突发传输的波形采样数据临时存储在输入缓冲器中，然后根据音调信息从缓冲器中读出，以产生所需音调的音调波形数据。数据块的突发传输和随后的音调波形数据生成以预定的再现采样周期异步地高速地执行。所产生的乐音波形数据通过预定再现采样周期中的输出数据输出。为了提高可再现间距的上限，而不需要增加输入缓冲器的容量，原始波形采样数据的薄化版本也可以预先存储在主存储器中，使得可以选择变薄的波形采样数据以允许升高上限。或者，可以通过使原始波形采样数据变薄而不是预先存储在主存储器中来产生这种变薄的波形采样数据。

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