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1. 发明授权

US06272465B1 Monolithic PC audio circuit 失效
标题翻译：单片PC音频电路
公开(公告)号：US06272465B1
公开(公告)日：2001-08-07
申请号：US08934969
申请日：1997-09-22
申请人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： Larry D. Hewitt , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Michael Hogan , Alfredo R. Linz , David Norris , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G10L500
CPC分类号： H03K23/68 , G06F3/162 , G06F7/026 , G06F9/3869 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H7/02 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.
摘要翻译：用于在个人计算机中提供增强音频性能的单片集成电路。单片电路包括波形合成器; 全功能立体声编解码电路，包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

2. 发明授权

US5659466A Monolithic PC audio circuit with enhanced digital wavetable audio synthesizer 失效
公开(公告)号：US5659466A
公开(公告)日：1997-08-19
申请号：US333536
申请日：1994-11-02
申请人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
发明人： David Norris , Jeffrey M. Blumenthal , Geoffrey E. Brehmer , Glen W. Brown , Carlin Dru Cabler , Ryan Feemster , David Guercio , Dale E. Gulick , Larry D. Hewitt , Michael Hogan , Alfredo R. Linz , Paul G. Schnizlein , Martin P. Soques , Michael E. Spak , David N. Suggs , Alan T. Torok
IPC分类号： G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2230/035 , G10H2240/311 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

3. 发明授权

US5648778A Stereo audio CODEC 失效
标题翻译：立体声音频编解码器
公开(公告)号：US5648778A
公开(公告)日：1997-07-15
申请号：US683754
申请日：1996-07-17
申请人： Alfredo R. Linz , Carlin Dru Cabler , Glen W. Brown , Martin P. Soques
发明人： Alfredo R. Linz , Carlin Dru Cabler , Glen W. Brown , Martin P. Soques
IPC分类号： F02B75/02 , G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , H03K23/68 , H03M7/32 , H03M1/00
CPC分类号： H03K23/68 , G06F3/162 , G10H1/0058 , G10H1/0066 , G10H1/125 , G10H7/002 , F02B2075/027 , G10H2230/035 , G10H2240/311 , G10H2250/115 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/611
摘要： A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.
摘要翻译：立体声音频CODEC，包括用于执行D / A和A / D转换的装置，用于在衰减/增益变化期间减少数字感应噪声的装置，数据格式转换装置，模拟和数字滤波装置，模拟混合装置，片上16- 采样，32位宽记录和播放FIFO，与外部串行DSP的串行接口，用于补充片上记录和播放FIFO，控制寄存器，寄存器数据总线和合成器DAC的大型本地存储器。

4. 发明授权

US5646621A Delta-sigma ADC with multi-stage decimation filter and gain compensation filter 失效
标题翻译：具有多级抽取滤波器和增益补偿滤波器的Delta-sigma ADC
公开(公告)号：US5646621A
公开(公告)日：1997-07-08
申请号：US333535
申请日：1994-11-02
申请人： Carlin Dru Cabler , Alfredo R. Linz
发明人： Carlin Dru Cabler , Alfredo R. Linz
IPC分类号： G06F7/02 , H03K23/68 , H03M3/04 , H03M3/00
CPC分类号： G06F7/026 , H03K23/68 , H03M3/344 , H03M3/462
摘要： An analog-to-digital conversion circuit is described which includes a front end sigma-delta modulator circuit, a multi-stage digital decimation filter circuit, and a digital compensation filter circuit. An overrange detect circuit is also provided.
摘要翻译：描述了包括前端Σ-Δ调制器电路，多级数字抽取滤波器电路和数字补偿滤波器电路的模拟 - 数字转换电路。还提供超量程检测电路。

5. 发明授权

US5995030A Apparatus and method for a combination D/A converter and FIR filter employing active current division from a single current source 失效
标题翻译：用于组合D / A转换器和FIR滤波器的装置和方法，其采用来自单个电流源的有源电流分配
公开(公告)号：US5995030A
公开(公告)日：1999-11-30
申请号：US526834
申请日：1995-09-12
申请人： Carlin Dru Cabler
发明人： Carlin Dru Cabler
IPC分类号： H03H17/02 , H03H17/06 , H03M1/74 , H03M3/02 , H03M1/66
CPC分类号： H03H17/0289 , H03M1/745 , H03M3/504
摘要： An active current steering semi-digital FIR filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of current paths, where each path includes an active element, such as a transistor, having a relatively high output impedance, which is connected to a common current source, and to an op amp for current-to-voltage conversion. The relatively high output impedance of the active current steering element causes any error term resulting from offset at the op amp inputs to be minimized.
摘要翻译：一种用于数模转换电路的有源电流转向半数字FIR滤波器，其包括具有1位数字输入流和多个输出抽头的移位寄存器，其中每个输出抽头提供1位信号，具有逻辑1或逻辑0的值，以及多个电流路径，其中每个路径包括连接到公共电流源的具有相对较高输出阻抗的有源元件，例如晶体管，并且用于电流至电压转换的运算放大器。有源电流导向元件的相对高的输出阻抗导致由运算放大器输入端的偏移导致的任何误差项都被最小化。

6. 发明授权

US5796851A Digital method to eliminate power-on pops and clicks 失效
标题翻译：数字方式消除上电弹出和点击
公开(公告)号：US5796851A
公开(公告)日：1998-08-18
申请号：US760760
申请日：1996-12-05
申请人： Larry Hewitt , Carlin Dru Cabler
发明人： Larry Hewitt , Carlin Dru Cabler
IPC分类号： H03G3/34 , H03M1/08 , H03M1/66 , H04B15/00
CPC分类号： H03M1/0881 , H03G3/348 , H03M1/66
摘要： A personal computer audio system is presented with a mechanism for digitally regulating the rate of voltage change of an audio output signal In one embodiment, the audio output signal from an integrated circuit is provided by means of a two-state audio amplifier. The first state of the amplifier is a high impedance state which exists prior to power-on and is maintained until an enable signal is asserted. When the enable signal is asserted, the amplifier drives the audio output signal line. Prior to the transition from the first to second states, a D/A converter is used to provide a ramp signal from the minimum voltage to the nominal operating voltage. The state transition is then initiated during the initial portion of the ramp signal.
摘要翻译：具有用于数字调节音频输出信号的电压变化速率的机构的个人计算机音频系统。在一个实施例中，来自集成电路的音频输出信号通过双状态音频放大器提供。放大器的第一状态是在上电之前存在的高阻抗状态，并且保持到使能信号被断言为止。当使能信号置位时，放大器驱动音频输出信号线。在从第一状态转换到第二状态之前，使用D / A转换器来提供从最小电压到标称工作电压的斜坡信号。然后在斜坡信号的初始部分期间启动状态转换。

7. 发明授权

US5648779A Sigma-delta modulator having reduced delay from input to output 失效
标题翻译： Sigma-delta调制器具有从输入到输出的延迟降低
公开(公告)号：US5648779A
公开(公告)日：1997-07-15
申请号：US352665
申请日：1994-12-09
申请人： Carlin Dru Cabler
发明人： Carlin Dru Cabler
IPC分类号： H03M3/02 , H03M7/00
CPC分类号： H03M7/3006 , H03M3/418 , H03M7/3022
摘要： Described herein is a fourth-order sigma-delta modulator which utilizes two second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators having a 1/2 sample period delay from input to output. A second-order sigma-delta modulator, including such integrators, exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator, which includes two such second-order sigma-delta modulators, exhibits a delay of two sample periods from input to output. The present sigma-delta modulator can be fabricated using switched capacitor circuitry to form an A/D convertor, and in another embodiment can be used as a digital noise shaper for a D/C convertor circuit. The 1/2 unit delay is implemented without requiring two D-flip flops in series, which results in a design and manufacturing advantage.
摘要翻译：这里描述的是利用连接在一起的两个二阶Σ-Δ调制器的四阶Σ-Δ调制器。每个二阶Σ-Δ调制器的特征在于包括具有从输入到输出的+ E，fra 1/2 + EE采样周期延迟的积分器。包括这种积分器的二阶Σ-Δ调制器表现出从输入到输出的单个采样周期延迟。包括两个这样的二阶Σ-Δ调制器的四阶Σ-Δ调制器表现出从输入到输出的两个采样周期的延迟。可以使用开关电容器电路来制造现有的Σ-Δ调制器以形成A / D转换器，并且在另一实施例中可以将其用作D / C转换器电路的数字噪声整形器。 + E，fra 1/2 + EE单位延迟实现，而不需要两个D触发器串联，这导致设计和制造优势。

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