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1. 发明授权

US5940610A Using prioritized interrupt callback routines to process different types of multimedia information 失效
标题翻译：使用优先级中断回调例程处理不同类型的多媒体信息
公开(公告)号：US5940610A
公开(公告)日：1999-08-17
申请号：US720891
申请日：1996-10-03
申请人： David C. Baker , Michael D. Asal , Jonathan I. Siann , Paul B. Wood , Jeffrey L. Nye , Stephen G. Glennon , Matthew D. Bates
发明人： David C. Baker , Michael D. Asal , Jonathan I. Siann , Paul B. Wood , Jeffrey L. Nye , Stephen G. Glennon , Matthew D. Bates
IPC分类号： G09G5/02 , G09G5/08 , G09G5/36 , G09G5/395 , H04N5/44 , G06F13/00
CPC分类号： G09G5/363 , G09G5/08 , G09G5/395 , G09G2340/125 , G09G5/02 , H04N5/4401
摘要： Multimedia information (e.g. graphics, video, sound, control information) passes through a system bus from a CPU main memory to a display memory in accordance with CPU commands. The information may be packetized with associated packet types identifying the different media. A media stream controller processes the information and passes the processed information to the display memory. Controllers in the media stream controller individually pass multimedia information to the display memory. A PACDAC controller in the media stream controller causes media (e.g. graphics, video) in the display memory to be transferred to a PACDAC for display. The format, sequence, and rate of this transfer may be flexibly controlled by software on a frame by frame basis. Arbitration logic establishes priorities for the different controllers in the media stream controller so they may share a single bus for accessing the display memory. A single interrupt controller coordinates interrupts (e.g. at a single level) to provide priorities based upon the type of interrupt cause or media. Each interrupt cause activates only the appropriate callback functions. Two different virtual machine sessions (e.g. Windows, DOS) share an interrupt line to process interrupt requests form one (1) session (e.g. Windows) before processing interrupt requests from the other.
摘要翻译：多媒体信息（例如，图形，视频，声音，控制信息）根据CPU命令从CPU主存储器传递到显示存储器。该信息可以用识别不同媒体的相关联的分组类型来分组。媒体流控制器处理信息并将处理的信息传递到显示存储器。媒体流控制器中的控制器将多媒体信息单独传递到显示存储器。媒体流控制器中的PACDAC控制器使显示存储器中的媒体（例如，图形，视频）被传送到PACDAC进行显示。该传输的格式，顺序和速率可以由软件在逐帧的基础上灵活地控制。仲裁逻辑为媒体流控制器中的不同控制器确定优先级，因此它们可以共享用于访问显示存储器的单个总线。单个中断控制器协调中断（例如在单个级别），以根据中断原因或介质的类型提供优先级。每个中断原因仅激活适当的回调函数。在处理来自另一个的中断请求之前，两个不同的虚拟机会话（例如Windows，DOS）共享中断线来处理从一（1）个会话（例如Windows）的中断请求。

2. 发明授权

US5715437A System for, and method of, processing in hardware commands received from software without polling of the hardware by the software 失效
标题翻译：从软件接收的硬件命令的处理系统和方法，而不用软件轮询硬件
公开(公告)号：US5715437A
公开(公告)日：1998-02-03
申请号：US337939
申请日：1994-11-10
申请人： David C. Baker , Michael D. Asal
发明人： David C. Baker , Michael D. Asal
IPC分类号： G06F3/153 , G06F9/24 , G06F9/38 , G06T11/00 , G09G5/36 , G06T1/60 , G06F15/76
CPC分类号： G06F9/3814 , G06F9/24 , G06F9/3802 , G06F9/3879
摘要： A CPU introduces software commands to a first limited capacity memory (e.g. FIFO), on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g. FIFO) of the second memory may also store commands normally passing from the CPU through the first memory. When the first memory becomes full, the commands may pass from the CPU through the second portion of the second memory (which may have a storage capacity considerably greater than that of the first memory) and then through the first memory. The commands may continue to flow in this auxiliary path until the second portion of the second memory becomes empty. A third memory of a limited capacity on the chip may pass the commands from the CPU to the first memory in the normal operation or to the second portion of the second memory when the first memory becomes full. The CPU may also pass commands to other peripheral equipment while a ready line is high. When low, the ready line prevents commands from passing to the peripheral equipment while the third memory is full. However, a command may pass from the third memory to the first or second memory to make the ready line high. A counter indicates the number of commands in the first and third memories and the second portion of the second memory. Software occasionally interrogates the counter to update in the software the number of commands in the counter.
摘要翻译： CPU将集成电路芯片上的软件命令引入第一有限容量存储器（例如FIFO）。根据这样的命令来处理来自第二存储器（离线芯片）的第一部分的数据（例如图形）。第二存储器的第二部分（例如FIFO）也可以存储正常地从CPU通过第一存储器的命令。当第一存储器变满时，命令可以从CPU通过第二存储器的第二部分（其可能具有明显大于第一存储器的存储容量），然后通过第一存储器。这些命令可以在该辅助路径中继续流动，直到第二个存储器的第二部分变空。当第一存储器变满时，芯片上的有限容量的第三存储器可以在正常操作中将命令从CPU传送到第一存储器，或者在第一存储器变满时将其传递到第二存储器的第二部分。当准备好的线路高时，CPU也可以将命令传递给其他外围设备。当为低电平时，就绪线路防止命令在第三个存储器已满时传递到外围设备。然而，命令可以从第三存储器传递到第一或第二存储器，以使就绪行高。计数器指示第一和第三存储器和第二存储器的第二部分中的命令的数量。软件偶尔询问计数器，在软件中更新计数器中的命令数。

3. 发明授权

US07698544B2 Automatic halting of a processor in debug mode due to reset 有权
标题翻译：由于复位，在调试模式下自动停止处理器
公开(公告)号：US07698544B2
公开(公告)日：2010-04-13
申请号：US11383212
申请日：2006-05-14
申请人： Anthony J. Lell , Michael D. Asal , Gary L. Swoboda
发明人： Anthony J. Lell , Michael D. Asal , Gary L. Swoboda
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： G06F1/24
摘要： Disclosed herein is a system and method of operating a processor before and after a reset has been asserted. Prior to a reset being asserted the processor operates in one of a plurality of states wherein primary code may be executed by the processor depending on said state. Upon a reset being asserted the processor begins executing code for a reset routine. The processor also executes a process such that the processor operates in the same state it was in prior to the reset upon the reset no longer being asserted.
摘要翻译：这里公开了一种在重置已经被断言之前和之后操作处理器的系统和方法。在复位被断言之前，处理器以多种状态之一运行，其中主代码可以由处理器根据所述状态执行。当复位被置位时，处理器开始执行复位例程的代码。处理器还执行处理，使得处理器在复位后不再被断言的情况下处于与复位之前相同的状态。

4. 发明授权

US5636335A Graphics computer system having a second palette shadowing data in a first palette 失效
标题翻译：图形计算机系统具有在第一调色板中的第二调色板阴影数据
公开(公告)号：US5636335A
公开(公告)日：1997-06-03
申请号：US479478
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06T15/60
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory. The second palette is connected to the graphics processor permitting it to specify the color data words stored in the second look-up table memory. An interface circuit connects to the host data bus, the host address bus and the second palette. The interface circuit writes data received from the host data bus into the second palette upon detecting predetermined addresses on the host address bus. This causes at least a portion of the second palette to store identical data as stored in corresponding locations of the first palette.
摘要翻译：包括主计算机和图形处理器的图形计算机系统。主机具有主机数据总线和主机地址总线。第一视频存储器存储与显示相对应的颜色代码。第一个视频存储器连接到主机，允许它指定颜色代码。连接到第一视频存储器的第一调色板具有第一查找表存储器，用于调用与从第一视频存储器接收的彩色代码相对应的彩色数据字。第一调色板连接到主计算机，允许其指定存储在第一查找表存储器中的颜色数据字。图形处理器具有本地数据总线和本地地址总线。第二视频存储器存储与显示相对应的颜色代码，图形处理器指定存储在第二视频存储器中的颜色代码。连接到第二视频存储器的第二调色板具有第二查找表存储器。第二调色板连接到图形处理器，允许其指定存储在第二查找表存储器中的颜色数据字。接口电路连接到主机数据总线，主机地址总线和第二个调色板。接口电路在检测到主机地址总线上的预定地址时，将从主机数据总线接收的数据写入第二调色板。这导致第二调色板的至少一部分存储与存储在第一调色板的相应位置中相同的数据。

5. 发明授权

US5627568A Display buffer using minimum number of VRAMs 失效
标题翻译：显示缓冲区使用最小数量的VRAM
公开(公告)号：US5627568A
公开(公告)日：1997-05-06
申请号：US990971
申请日：1992-12-15
申请人： Ian J. Sherlock , Richard D. Simpson , Michael D. Asal
发明人： Ian J. Sherlock , Richard D. Simpson , Michael D. Asal
IPC分类号： G09G5/36 , G09G5/39 , G09G5/00
CPC分类号： G09G5/39 , G09G5/363
摘要： A display buffer includes a plurality of memory banks, each said bank having a plurality of ordered rows of data storage locations. Circuitry controls the storage of a plurality of sequenced lines of display data in said display buffer. A first set of lines of display data is stored at contiguous locations in a first memory bank with the first word of a first line being stored in a location offset from the first location of the first row so a last word of a last line is stored in the last location of the last row. A second set of lines is stored at contiguous locations starting at the first row of the second memory bank. A last line of the second set of lines is stored so that the last word of this last line is stored in the last location of a selected row of the second bank. A third set of lines is stored in a third memory bank starting at a memory line other than the first memory line. If additional space is needed, the display lines wrap around to the first location of the first line of the third bank of memories. A graphics processor may provide the memory addressing and bank selection logic.
摘要翻译：显示缓冲器包括多个存储体，每个所述存储体具有多个排列的数据存储位置行。电路控制在所述显示缓冲器中存储多条排序的显示数据行。第一组显示数据被存储在第一存储体中的连续位置处，其中第一行的第一个字被存储在偏离第一行的第一位置的位置中，从而最后一行的最后一个字被存储在最后一行的最后一个位置。第二组线路存储在从第二存储器组的第一行开始的连续位置处。存储第二组行的最后一行，使得最后一行的最后一个字被存储在第二组的所选行的最后位置。第三组线路存储在从第一存储器线以外的存储线开始的第三存储体中。如果需要额外的空间，则显示线缠绕到第三组存储器的第一行的第一位置。图形处理器可以提供存储器寻址和存储体选择逻辑。

6. 发明授权

US5341470A Computer graphics systems, palette devices and methods for shift clock pulse insertion during blanking 失效
标题翻译：计算机图形系统，调色板设备和消隐时移位时钟脉冲插入的方法
公开(公告)号：US5341470A
公开(公告)日：1994-08-23
申请号：US544779
申请日：1990-06-27
申请人： Richard D. Simpson , Jeffrey L. Nye , Michael D. Asal
发明人： Richard D. Simpson , Jeffrey L. Nye , Michael D. Asal
IPC分类号： G09G5/02 , G09G5/06 , G09G5/12 , G09G5/36 , G09G5/39 , G06F15/62
CPC分类号： G09G5/12 , G09G5/06 , G09G5/363 , G09G5/39 , G09G2330/12 , G09G2360/123 , G09G5/022
摘要： A computer graphics system. The system includes a video memory having a shift register adapted for split shift register transfers, and digital computer for controlling the video memory and having a tap point counter clocked by a shift clock signal and also having a blanking circuit with a blanking output. Further, logic circuitry enabled by the blanking output is connected to initiate an extra shift clock pulse for the tap point counter during a blanking interval. Other systems, palette devices, and methods are also disclosed.
摘要翻译：计算机图形系统。该系统包括具有适用于分离移位寄存器传输的移位寄存器的视频存储器，以及用于控制视频存储器并具有由移位时钟信号计时的分接点计数器的数字计算机，并且还具有带有消隐输出的消隐电路。此外，由消隐输出使能的逻辑电路被连接以在消隐间隔期间启动分接点计数器的额外移位时钟脉冲。还公开了其他系统，调色板装置和方法。

7. 发明授权

US5142621A Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers 失效
标题翻译：具有分别在像素位置寄存器的X和Y坐标上操作的指令的图形处理装置
公开(公告)号：US5142621A
公开(公告)日：1992-08-25
申请号：US498457
申请日：1990-03-21
申请人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
IPC分类号： G06F9/345 , G06F9/38 , G06F15/78 , G06T1/20
CPC分类号： G06T1/20 , G06F15/7857 , G06F9/345 , G06F9/3885
摘要： The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.
摘要翻译：本发明的图形处理装置利用寄存器文件的各个寄存器来存储像素的X和Y坐标。这些X和Y坐标虽然形成单个数据字，但是可以通过例如具有指定Y坐标的最高有效位和指定Y坐标的最低有效位来分离。图形处理装置支持提供对这些X和Y坐标的单独且独立的数据操纵的指令。这些X Y坐标操作指令可以为两个数据字提供单独的X Y算术运算，分别进行X和Y比较运算，单独的X和Y数据移动操作以及X Y地址格式与线性地址格式之间的转换。该技术对于使用位映射图形的可视显示系统中的X Y地址坐标的操纵非常有用。

8. 发明授权

US5923340A Process of processing graphics data 失效
标题翻译：处理图形数据的过程
公开(公告)号：US5923340A
公开(公告)日：1999-07-13
申请号：US485540
申请日：1995-06-07
申请人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
IPC分类号： G06T1/20 , G09G5/393 , G06F12/06
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may by simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译：本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。第一数据寄存器存储一组X和Y坐标。在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。预定的颜色代码优选地存储在另一个数据寄存器中。通过适当选择存储在第二数据寄存器中的X和Y坐标数据，X或Y坐标可以单独改变，或者两者可以同时改变。在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。该指令用于提高在位映射显示中绘制线或计算曲线的速度。

9. 发明授权

US5546553A Multifunctional access devices, systems and methods 失效
公开(公告)号：US5546553A
公开(公告)日：1996-08-13
申请号：US359324
申请日：1994-12-15
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/00
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

10. 发明授权

US5437011A Graphics computer system, a graphics system arrangement, a display system, a graphics processor and a method of processing graphic data 失效
标题翻译：图形计算机系统，图形系统布置，显示系统，图形处理器和处理图形数据的方法
公开(公告)号：US5437011A
公开(公告)日：1995-07-25
申请号：US191885
申请日：1994-02-04
申请人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
IPC分类号： G06T1/20 , G09G5/393 , G06F15/00
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored In a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first data register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented or decremented. This instruction serves to enhance the speed at which a line or computed curve may be drawn in the bit mapped display.
摘要翻译：本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。第一数据寄存器存储一组X和Y坐标。在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。然后，存储在第一数据寄存器中的X和Y坐标通过添加存储在第二数据寄存器中的X和Y坐标来提前。第二实施例是类似的，除了存储在第一数据寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。预定的颜色代码优选地存储在另一个数据寄存器中。通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。在第二个寄存器中提供有符号的X和Y坐标值可使X或Y坐标值递增或递减。该指令用于增强在位映射显示中绘制线或计算曲线的速度。

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