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1. 发明授权

US09767070B2 Storage system with a memory blade that generates a computational result for a storage device 有权
公开(公告)号：US09767070B2
公开(公告)日：2017-09-19
申请号：US12613537
申请日：2009-11-06
申请人： Jichuan Chang , Kevin T Lim , Parthasarathy Ranganathan
发明人： Jichuan Chang , Kevin T Lim , Parthasarathy Ranganathan
IPC分类号： G06F15/167 , G06F15/78
CPC分类号： G06F15/7803 , G06F15/7857 , G06F15/786
摘要： One embodiment is a storage system having one or more compute blades to generate and use data and one or more memory blades to generate a computational result. The computational result is generated by a computational function that transforms the data generated and used by the one or more compute blades. One or more storage devices are in communication with and remotely located from the one or more compute blades. The one or more storage devices store and serve the data for the one or more compute blades.

2. 发明申请

US20130262793A1 SPLIT-WORD MEMORY 有权
标题翻译：分词记忆
公开(公告)号：US20130262793A1
公开(公告)日：2013-10-03
申请号：US13436745
申请日：2012-03-30
申请人： Lutz NAETHKE , Axel BORKOWSKI , Bert BRETSCHNEIDER , Kyriakos A. STAVROU , Rainer THEUER
发明人： Lutz NAETHKE , Axel BORKOWSKI , Bert BRETSCHNEIDER , Kyriakos A. STAVROU , Rainer THEUER
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30185 , G06F9/30192 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3887 , G06F9/3889 , G06F12/00 , G06F12/04 , G06F12/0607 , G06F12/0846 , G06F12/0862 , G06F12/0875 , G06F15/7807 , G06F15/7857 , G06F2212/452 , G06F2212/6028 , Y02D10/12 , Y02D10/13
摘要： Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.
摘要翻译：有效地存储，读取和/或处理单词数据音节的方法，过程和装置。包括多个音节的数据字的一部分可以被计算机处理器读取。处理器可以从第一存储器读取数据字的第一个音节。处理器可以从存储器的第二部分读取数据字的第二个音节。第二个音节可以包括比第一个音节的位不太关键的比特。第二存储器可以基于一个或多个物理属性与第一存储器不同。

3. 发明申请

US20070186079A1 DIGITAL SIGNAL PROCESSOR WITH VARIABLE LENGTH INSTRUCTION SET 有权
标题翻译：具有可变长度指令集的数字信号处理器
公开(公告)号：US20070186079A1
公开(公告)日：2007-08-09
申请号：US11535005
申请日：2006-09-25
申请人： Gilbert Sih , Qiuzhen Zou , Jian Lin
发明人： Gilbert Sih , Qiuzhen Zou , Jian Lin
IPC分类号： G06F9/30
CPC分类号： G06F9/30109 , G06F9/30014 , G06F9/30032 , G06F9/30043 , G06F9/30141 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3826 , G06F9/3853 , G06F9/3885 , G06F9/3893 , G06F12/04 , G06F15/7857
摘要： A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.
摘要翻译：数字信号处理器使用可变长度指令集。可变长度指令可以存储在存储器空间内的相邻位置。指令的开始和结束可以但不是要求跨越存储器字边界发生。优选地，可变长度指令包含可变数目的指令片段。每个指令片段导致执行特定的操作（或操作），从而允许在每个时钟周期期间执行多个操作。这减少了执行任务所需的总时钟周期数。

4. 发明申请

US20070043886A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070043886A1
公开(公告)日：2007-02-22
申请号：US11589840
申请日：2006-10-31
申请人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
发明人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
IPC分类号： G06F13/28
CPC分类号： G06F12/0692 , G06F15/7857
摘要： A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
摘要翻译：半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。

5. 发明申请

US20040199558A1 DSP execution unit for efficient alternate modes of operation 有权
标题翻译： DSP执行单元，用于高效的交替操作模式
公开(公告)号：US20040199558A1
公开(公告)日：2004-10-07
申请号：US10828913
申请日：2004-04-20
发明人： Bradley C. Aldrich , Jose Fridman , Paul Meyer , Gang Liang
IPC分类号： G06F007/38
CPC分类号： G06F7/5324 , G06F7/509 , G06F7/57 , G06F9/30014 , G06F15/7857 , G06F2207/382 , G06F2207/3828
摘要： In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using multiple components or may share components. When the processing paths share components, only one of the processing paths may be used at a time.
摘要翻译：在一个实施例中，数字信号处理器（DSP）处理n位数据和（n / 2）位数据。 DSP包括多个处理路径。第一处理路径处理n位数据。第二处理路径是进程（n / 2）位数据。可以使用多个组件来建立多个处理路径，或者可以共享组件。当处理路径共享组件时，一次只能使用一个处理路径。

6. 发明申请

US20040030844A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20040030844A1
公开(公告)日：2004-02-12
申请号：US10624598
申请日：2003-07-23
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
IPC分类号： G06F012/00
CPC分类号： G06F12/0692 , G06F15/7857
摘要： A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
摘要翻译：半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。

7. 发明申请

US20030208674A1 Digital signal processor with variable length instruction set 审中-公开
标题翻译：具有可变长度指令集的数字信号处理器
公开(公告)号：US20030208674A1
公开(公告)日：2003-11-06
申请号：US10269776
申请日：2002-10-11
发明人： Gilbert C. Sih , Qiuzhen Zou , Jian Lin
IPC分类号： G06F009/30
CPC分类号： G06F9/30109 , G06F9/30014 , G06F9/30032 , G06F9/30043 , G06F9/30141 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3826 , G06F9/3853 , G06F9/3885 , G06F9/3893 , G06F12/04 , G06F15/7857
摘要： A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.
摘要翻译：数字信号处理器使用可变长度指令集。可变长度指令可以存储在存储器空间内的相邻位置。指令的开始和结束可以但不是要求跨越存储器字边界发生。优选地，可变长度指令包含可变数目的指令片段。每个指令片段导致执行特定的操作（或操作），从而允许在每个时钟周期期间执行多个操作。这减少了执行任务所需的总时钟周期数。

8. 发明申请

US20030005261A1 Method and apparatus for attaching accelerator hardware containing internal state to a processing core 审中-公开
标题翻译：用于将包含内部状态的加速器硬件附接到处理核心的方法和装置
公开(公告)号：US20030005261A1
公开(公告)日：2003-01-02
申请号：US09896423
申请日：2001-06-29
发明人： Gad Sheaffer
IPC分类号： G06F015/00
CPC分类号： G06F9/3877 , G06F9/3824 , G06F15/7857
摘要： A digital signal processor system and method for improving processing speed by providing a memory file and a register file connected to an accelerator which is connected to a write-back logic bus. One or more execution units can be connected between the memory and register files and the accelerator and/or between the accelerator and the bus. The accelerator is provided with internal state. The internal state is configured to enable increasing the ratio of computation operations to the memory bandwidth available from a digital signal processor.
摘要翻译：一种数字信号处理器系统和方法，用于通过提供连接到与回写逻辑总线连接的加速器的存储器文件和寄存器文件来提高处理速度。一个或多个执行单元可以连接在存储器和寄存器文件以及加速器和/或加速器和总线之间。加速器配有内部状态。内部状态被配置为能够增加计算操作与从数字信号处理器可用的存储器带宽的比率。

9. 发明授权

US06125438A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06125438A
公开(公告)日：2000-09-26
申请号：US63009
申请日：1998-04-21
申请人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
发明人： Tadashi Okamoto , Hiroshi Kadota , Yoshiteru Mino
IPC分类号： G06F15/78 , G06F15/00
CPC分类号： G06F15/7857 , G06F15/7864
摘要： A data processor of the invention includes plural memories, plural arithmetic units, a data transfer unit and a network. The data transfer unit transfers various data to predetermined memories, and switches the connections between the memories and the arithmetic units by using the network. The control unit adds a processability judgement signal to a data read from a predetermined memory in reading the data, so as to make a pair of the data and the processability judgement signal. Each of the arithmetic units receives the data and the processability judgement signal, conducts predetermined processing on the received data, delays the received processability judgement signal by the number of cycles equal to its own processing cycle, and outputs resultant data obtained through the processing and the delayed processability judgement signal. Accordingly, in storing ultimate resultant data in a predetermined storage unit, the storage unit stores the ultimate resultant data as effective data on the basis of the processability judgement signal added to the resultant data. The data processor attains wide application and can be applied to various types of multimedia applications by switching the connections between the memories and the arithmetic units by using the network.
摘要翻译：本发明的数据处理器包括多个存储器，多个运算单元，数据传送单元和网络。数据传送单元将各种数据传送到预定存储器，并且通过使用网络来切换存储器和算术单元之间的连接。控制单元在读取数据时，对从预定存储器读取的数据添加可处理性判断信号，以便形成一对数据和加工性判定信号。每个算术单元接收数据和可处理性判断信号，对接收到的数据进行预定的处理，将接收到的加工性判断信号延迟等于其自身的处理周期的周期数，并输出通过处理获得的结果数据和延迟加工性判断信号。因此，在将最终结果数据存储在预定存储单元中时，存储单元基于加到结果数据的加工性判断信号将最终结果数据存储为有效数据。数据处理器具有广泛的应用，可以通过使用网络切换存储器和算术单元之间的连接来应用于各种类型的多媒体应用。

10. 发明授权

US6032247A Central processing unit including APX and DSP cores which receives and processes APX and DSP instructions 失效
标题翻译：中央处理单元包括接收和处理APX和DSP指令的APX和DSP内核
公开(公告)号：US6032247A
公开(公告)日：2000-02-29
申请号：US969865
申请日：1997-11-14
申请人： Saf Asghar , Andrew Mills
发明人： Saf Asghar , Andrew Mills
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/78 , G06F15/00
CPC分类号： G06F9/3836 , G06F15/7857 , G06F9/30174 , G06F9/30189 , G06F9/382 , G06F9/3822 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.
摘要翻译：包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。在第一实施例中，CPU接收诸如X86指令的通用指令，其中某些X86指令序列实现DSP功能。 CPU包括处理器模式寄存器，其被写入一个或多个处理器模式位以指示指令序列是否实现DSP功能。 CPU还包括智能DSP功能解码器或预处理器，它检查处理器模式位，并确定DSP功能是否正在执行。如果通过指令序列实现DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。如果处理器模式位指示指令存储器中的X86指令不实现DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。在第二实施例中，CPU接收包括X86指令和DSP指令的指令序列。处理器模式寄存器用一个或多个处理器模式位写入，以指示指令序列是否包括X86或DSP指令，并将指令相应地路由到X86内核或DSP内核。

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