专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5287100A Graphics systems, palettes and methods with combined video and shift clock control 失效
标题翻译：图形系统，调色板和具有组合视频和移位时钟控制的方法
公开(公告)号：US5287100A
公开(公告)日：1994-02-15
申请号：US545424
申请日：1990-06-27
申请人： Karl M. Guttag , Jeffrey L. Nye , Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Michael D. Asal
发明人： Karl M. Guttag , Jeffrey L. Nye , Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Michael D. Asal
IPC分类号： G09G5/02 , G09G5/06 , G09G5/12 , G09G5/36 , G09G5/39 , G09G5/00
CPC分类号： G09G5/363 , G09G5/06 , G09G5/12 , G09G5/39 , G09G2330/12 , G09G2360/02 , G09G2360/123 , G09G5/022
摘要： An integrated circuit for use with a plurality of clock oscillators. The integrated circuit has a semiconductor chip, function performing circuitry fabricated on the semiconductor chip and responsive to clock pulses provided thereto, and a semiconductor chip package having pins connected to the function performing circuitry. The integrated circuit further has a register accessible via the pins for external entry of clock control information. A clock control circuit responsive to the clock control information entered in said register has inputs connected to pins for the clock oscillators. The function performing circuitry is connected to the clock control circuit so that clock pulses are provided to the function performing circuitry by the clock control circuit in accordance with the clock control information entered in the register. Other integrated circuits, palette devices, computer graphics systems, printer systems and methods are also disclosed.
摘要翻译：一种用于多个时钟振荡器的集成电路。集成电路具有半导体芯片，功能执行电路，其制造在半导体芯片上并响应提供给其的时钟脉冲，以及具有连接到功能执行电路的引脚的半导体芯片封装。集成电路还具有可通过引脚访问的寄存器，用于外部输入时钟控制信息。响应于在所述寄存器中输入的时钟控制信息的时钟控制电路具有连接到时钟振荡器的引脚的输入。功能执行电路连接到时钟控制电路，使得时钟脉冲根据输入到寄存器中的时钟控制信息由时钟控制电路提供给功能执行电路。还公开了其他集成电路，调色板装置，计算机图形系统，打印机系统和方法。

2. 发明授权

US5162784A Graphics data processing apparatus with draw and advance operation 失效
标题翻译：图形数据处理设备带有绘制和提前操作
公开(公告)号：US5162784A
公开(公告)日：1992-11-10
申请号：US522409
申请日：1990-05-10
申请人： Karl M. Guttag , Mark F. Novak , Michael D. Asal , Neil Tebbutt , Jerry R. Van Aken
发明人： Karl M. Guttag , Mark F. Novak , Michael D. Asal , Neil Tebbutt , Jerry R. Van Aken
IPC分类号： G06T1/20 , G09G5/393
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to enhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译：本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。第一数据寄存器存储一组X和Y坐标。在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。预定的颜色代码优选地存储在另一个数据寄存器中。通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。该指令用于提高在位映射显示中绘制线或计算曲线的速度。

3. 发明授权

US06061711A Efficient context saving and restoring in a multi-tasking computing system environment 失效
标题翻译：在多任务计算系统环境中高效的上下文保存和恢复
公开(公告)号：US06061711A
公开(公告)日：2000-05-09
申请号：US699280
申请日：1996-08-19
申请人： Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Le T. Nguyen , Jerry R. Van Aken , Alessandro Forin , Andrew R. Raffman
发明人： Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Le T. Nguyen , Jerry R. Van Aken , Alessandro Forin , Andrew R. Raffman
IPC分类号： G06F9/44 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F17/16
CPC分类号： G06F9/30087 , G06F9/30003 , G06F9/30036 , G06F9/30043 , G06F9/3009 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3887 , G06F9/461
摘要： In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program. Unnecessarily saving and loading all available processor state information can be noticeably inefficient particularly where relatively large amounts of processor state information exists. In one embodiment, a processor requests a co-processor to context switch out the currently executing program. At a predetermined appropriate point in the executing program, the co-processor responds by halting program execution and saving only the minimal amount of processor state information necessary for successful restoration of the program. The appropriate point is chosen by the application programmer at a location in the executing program that requires preserving a minimal portion of the processor information across a context switch. By saving only a minimal amount of processor information, processor time savings are accumulated across context save and restoration operations.
摘要翻译：在多任务计算系统环境中，停止一个程序并上下文切换，使得处理器可以在后续程序中上下文切换以执行。存在反映正在上下文切换的程序的状态的处理器状态信息。该处理器状态信息的存储允许成功恢复上下文切换程序。当上下文切换程序随后进行上下文切换时，加载所存储的处理器信息以准备好在先前停止执行的点成功恢复程序。尽管可以将大面积的存储器分配给处理器状态信息存储，但是只有一部分可能需要在上下文切换中被保留以成功地保存和恢复上下文切换程序。不必要地保存和加载所有可用的处理器状态信息，特别是在存在相对大量的处理器状态信息的情况下是显着的。在一个实施例中，处理器请求协处理器上下文切换当前执行的程序。在执行程序中的预定的适当点处，协处理器通过停止程序执行并且仅节省成功恢复程序所需的最小量的处理器状态信息来进行响应。应用程序员在执行程序中需要在上下文切换中保留处理器信息的最小部分的位置来选择适当的点。通过仅节省最少量的处理器信息，可以在上下文保存和恢复操作中累积处理器时间节省。

4. 发明授权

US5923340A Process of processing graphics data 失效
标题翻译：处理图形数据的过程
公开(公告)号：US5923340A
公开(公告)日：1999-07-13
申请号：US485540
申请日：1995-06-07
申请人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
IPC分类号： G06T1/20 , G09G5/393 , G06F12/06
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may by simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译：本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。第一数据寄存器存储一组X和Y坐标。在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。预定的颜色代码优选地存储在另一个数据寄存器中。通过适当选择存储在第二数据寄存器中的X和Y坐标数据，X或Y坐标可以单独改变，或者两者可以同时改变。在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。该指令用于提高在位映射显示中绘制线或计算曲线的速度。

5. 发明授权

US5596519A Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR 失效
标题翻译：迭代分割装置，采用最左侧检测的系统和方法，最大限度地利用异或进行检测
公开(公告)号：US5596519A
公开(公告)日：1997-01-21
申请号：US484113
申请日：1995-06-07
申请人： Jerry R. Van Aken , Karl M. Guttag , Sydney W. Poland
发明人： Jerry R. Van Aken , Karl M. Guttag , Sydney W. Poland
IPC分类号： G06F7/52 , G06F7/74
CPC分类号： G06F7/74 , G06F7/535 , G06F2207/5353 , G06F7/49936
摘要： An iterative technique for division having a divisor of N bits and a numerator of more than N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator is left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. Next the divisor is subtracted from the N most significant bits of the numerator. If the difference is greater than or equal to zero, then the next quotient bit is "1" and the difference is substituted for the N most significant bits of the numerator. If the difference is less than zero, then the next quotient bit is "0". Then the numerator is left shifted one place. These iterations repeat until they exceed N. The last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are "0".
摘要翻译：一种用于除法的迭代技术，其具有N位的除数和大于N位的分子。每个迭代包括对分子的N个最高有效位的最左一位（1011,1035）的位置的初始检测。如果该L不为零，则分子左移L位（1016,1033），下一个L商位被设置为零，并且完成的迭代次数增加L.替代实施例检测位置留下分子和除数的N个最高有效位的异或的最多的一个。接下来，从分子的N个最高有效位中减去除数。如果差值大于或等于零，则下一个商位为“1”，差值代替分子的N个最高有效位。如果差值小于零，则下一个商位为“0”。然后分子左移一个位置。这些迭代重复直到它们超过N.最后一个分子是除法的剩余部分。这种技术消除了这种技术确定商位为“0”的情况下的无用数据操作。

6. 发明授权

US5437011A Graphics computer system, a graphics system arrangement, a display system, a graphics processor and a method of processing graphic data 失效
标题翻译：图形计算机系统，图形系统布置，显示系统，图形处理器和处理图形数据的方法
公开(公告)号：US5437011A
公开(公告)日：1995-07-25
申请号：US191885
申请日：1994-02-04
申请人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
IPC分类号： G06T1/20 , G09G5/393 , G06F15/00
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored In a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first data register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented or decremented. This instruction serves to enhance the speed at which a line or computed curve may be drawn in the bit mapped display.
摘要翻译：本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。第一数据寄存器存储一组X和Y坐标。在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。然后，存储在第一数据寄存器中的X和Y坐标通过添加存储在第二数据寄存器中的X和Y坐标来提前。第二实施例是类似的，除了存储在第一数据寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。预定的颜色代码优选地存储在另一个数据寄存器中。通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。在第二个寄存器中提供有符号的X和Y坐标值可使X或Y坐标值递增或递减。该指令用于增强在位映射显示中绘制线或计算曲线的速度。

7. 发明授权

US5371517A Video interface palette, systems and method 失效
标题翻译：视频界面调色板，系统和方法
公开(公告)号：US5371517A
公开(公告)日：1994-12-06
申请号：US791757
申请日：1991-11-08
申请人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
发明人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
IPC分类号： G06F11/00 , G09G5/06 , G09G5/18 , G09G1/28
CPC分类号： G06F11/006 , G09G5/06 , G09G5/18
摘要： A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.
摘要翻译：响应于在控制数据终端接收的主时钟选择控制字，调色板从在时钟输入端接收的多个时钟信号中选择主时钟。 A电路根据主时钟的选择的分频比形成多个分频的下降时钟信号。电路响应于在控制数据端子处接收的输出时钟选择控制字的至少一些位，从分频的下降时钟信号中选择移位时钟。电路响应于消隐数据选择性地启用和禁用移位时钟。响应于输出时钟选择控制字的至少一些位，电路从分频的下降时钟信号中选择视频时钟。电路将彩色码输入端子接收的彩色码的多位字与主时钟同步。响应于接收到颜色代码的每个多个位字，A电路输出至少一个存储器调用地址。电路将颜色数据字存储在具有相关联的存储器调用地址的多个数据存储位置中，并且在接收到相关联的存储器调用地址时输出彩色数据字。电路将彩色数据字选择性地写入这些多个位置。电路将视频控制终端接收的视频控制信号与主时钟同步，并提供消隐数据。电路选择所述颜色数据字和在所述颜色代码输入端接收的真彩色数据字之间的输出。

8. 发明授权

US5327159A Packed bus selection of multiple pixel depths in palette devices, systems and methods 失效
标题翻译：在调色板设备，系统和方法中的多个像素深度的压缩总线选择
公开(公告)号：US5327159A
公开(公告)日：1994-07-05
申请号：US116301
申请日：1993-09-03
申请人： Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Jeffrey L. Nye , Karl M. Guttag
发明人： Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Jeffrey L. Nye , Karl M. Guttag
IPC分类号： G09G5/06 , G09G1/28
CPC分类号： G09G5/06
摘要： A palette device controllable by a digital computer with a video memory having a bus for supplying multiple color codes for the palette device in each bus cycle. The palette device includes a multiple-bit input for entry of the color codes from the bus, and a look-up table memory for supplying color data words in response to the color codes from the input. Color code transfer circuitry is connected between the input and the look-up table memory to supply the look-up table memory from the input sequentially with color codes of selectable width packing the entire width of the bus. Improved palette devices, graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.
摘要翻译：可由具有视频存储器的数字计算机控制的调色板装置，其具有用于在每个总线周期中为调色板装置提供多个颜色代码的总线。调色板装置包括用于从总线输入颜色代码的多位输入，以及用于响应于来自输入的颜色代码提供彩色数据字的查找表存储器。颜色代码传输电路连接在输入和查找表存储器之间，以从输入中顺序地提供查找表存储器，其颜色代码可选择宽度包装总线的整个宽度。还公开了改进的调色板设备，图形计算机系统，传真系统，打印机系统和其他系统和方法。

9. 发明授权

US5025407A Graphics floating point coprocessor having matrix capabilities 失效
标题翻译：具有矩阵功能的图形浮点协处理器
公开(公告)号：US5025407A
公开(公告)日：1991-06-18
申请号：US387459
申请日：1989-07-28
申请人： David W. Gulley , Jerry R. Van Aken
发明人： David W. Gulley , Jerry R. Van Aken
IPC分类号： G06F9/302 , G06F9/38 , G06F15/78 , G06T17/00
CPC分类号： G06F9/30014 , G06F15/8076 , G06F9/3879 , G06T17/00
摘要： A graphics coprocessor designed to work in conjunction with a host graphic processor in a graphics system. The coprocessor is adapted to perform arithmetic calculations including matrix calculations. The matrix size is such that the intermediate results require more registers than are practical to include in the coprocessor. This has been solved by arranging for certain selected ones of the intermediate results to continue within the program execution from stage to stage and avoiding intermediate storage.
摘要翻译：设计用于与图形系统中的主机图形处理器协同工作的图形协处理器。协处理器适于执行包括矩阵计算在内的算术计算。矩阵尺寸使得中间结果需要比实际可包括在协处理器中更多的寄存器。这已经通过安排中间结果中的某些选定的一个在阶段到阶段的程序执行中继续并且避免中间存储来解决。

10. 发明授权

US5446482A Flexible graphics interface device switch selectable big and little endian modes, systems and methods 失效
标题翻译：灵活的图形界面设备开关选择大和小端模式，系统和方法
公开(公告)号：US5446482A
公开(公告)日：1995-08-29
申请号：US792503
申请日：1991-11-13
申请人： Jerry R. Van Aken , Chenwei J. Yin
发明人： Jerry R. Van Aken , Chenwei J. Yin
IPC分类号： G09G5/02 , G06T11/00 , G09G5/06 , G09G5/36 , G09G1/28
CPC分类号： G09G5/06
摘要： A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of data formatted in a preselected one of the big-endian and little-endian formats. An array of j sequentially ordered first AND gates 126 is provided, each first AND gate 126 having first and second input ports and an output port, the first input port of the n.sup.th first AND gate 126 coupled to the n.sup.th one of the input terminals, the second input ports of the first AND gates 126 coupled to a control signal. An array of j sequentially ordered second AND gates 128 are provided, and each second AND gate 128 having first and second input ports and an output port, of the first input port of an n.sup.th one of the second AND gates 128 coupled to a (j-n+1).sup.th one of the first input terminals, the second input ports of the second AND gates 128 are coupled to a second control. An array of j sequentially ordered OR gates 130 are provided each having first and second input ports and an output port, the first input port of an m.sup.th one of the OR gates 130 being coupled to the output of an m.sup.th one of the first AND gate 126, the second input port of an n.sup.th one of the OR gates 130 coupled to the output of the n.sup.th one of the second AND gates 128. Wherein j is a consonant, n is a variable between 1 and j, and m is a variable between 1 and j.
摘要翻译：提供一个电路83,97用于选择性地将从大端和小端格式选择的格式接收的数据解析为大端和小端格式的另一种格式，并且包括j个顺序数据输入的阵列用于接收以预选的大端和小端格式格式化的数据的j位字的终端。提供了j个顺序排列的第一与门126的阵列，每个第一与门126具有第一和第二输入端口和输出端口，第n个第一与门126的第一输入端口耦合到第n个输入端子，第一与门126的第二输入端口耦合到控制信号。提供了j个顺序排列的第二与门128的阵列，并且每个第二与门128具有第一和第二输入端口的第一和第二输入端口和第二输入端口，第二输入端口与第 -n + 1）个第一输入端，第二与门128的第二输入端耦合到第二控制。提供了具有第一和第二输入端口和输出端口的j个顺序OR门130的阵列，或门130的第m个的第一输入端口耦合到第一与门第一个的输出端 126是与第二AND门128的第n个的输出耦合的或门130中第n个的第二输入端口。其中j是辅音，n是1和j之间的变量，m是变量在1和j之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式