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1. 发明授权

US5546553A Multifunctional access devices, systems and methods 失效
公开(公告)号：US5546553A
公开(公告)日：1996-08-13
申请号：US359324
申请日：1994-12-15
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/00
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

2. 发明授权

US5247678A Load time linker for software used with a multiprocessor system 失效
标题翻译：用于与多处理器系统一起使用的软件的加载时间链接器
公开(公告)号：US5247678A
公开(公告)日：1993-09-21
申请号：US420491
申请日：1989-10-12
申请人： James G. Littleton
发明人： James G. Littleton
IPC分类号： G06F9/445
CPC分类号： G06F9/44521
摘要： A method used in a multiprocessor computer system for linking extended functions, which are to be called from an application program running on a host processor and executed by a subprocessor, to primitive functions to be executed by the subprocessor. The extended functions may be created independently of the primitive functions, collected in a special partially linked load module, stored, and dynamically linked to other code at run time of the application program.
摘要翻译：一种在多处理器计算机系统中用于将从主机处理器上运行并由子处理器执行的应用程序调用的扩展函数链接到由子处理器执行的原始函数的方法。扩展功能可以独立于在应用程序的运行时收集在特殊的部分链接的加载模块中的基本功能，存储并且动态地链接到其他代码。

3. 发明授权

US6154824A Multifunctional access devices, systems and methods 失效
标题翻译：多功能接入设备，系统和方法
公开(公告)号：US6154824A
公开(公告)日：2000-11-28
申请号：US474866
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/00
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.
摘要翻译：一种用于第一和第二数字计算机的多功能存取电路，每个数字计算机具有用于提供地址的地址总线和用于提供数据的数据总线。访问电路具有地址解码器，其具有用于来自第一计算机的地址总线的输入，以及地址转换器电路，其具有用于由第一计算机的地址总线提供的地址的地址输入，并将翻译的地址输出到第二计算机的地址总线。地址转换器电路还具有可由地址解码器和数据输入端选择的寄存器，用来从第一台计算机的数据总线的数据对所选择的寄存器进行编程。在访问电路中还有一个端口电路，具有由地址解码器控制的寄存器，用于从第一计算机的数据总线输入地址信息，并在第二计算机的地址总线上断言地址信息。此外，模式控制电路连接到地址解码器并连接到数据总线以对模式控制电路进行编程，以选择性地建立地址转换器电路和端口电路的操作。还描述了其他访问电路，设备，系统和方法。

4. 发明授权

US5696924A Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads 失效
标题翻译：具有地址转换的存储器访问电路在写入时执行翻译地址的自动增量，并在读取时返回到翻译的地址
公开(公告)号：US5696924A
公开(公告)日：1997-12-09
申请号：US487750
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/10
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.
摘要翻译：一种与具有地址总线，数据总线和一组控制线的图形处理器一起使用的存储器存取系统。连接到图形处理器的地址总线的地址转换器电路在从图形处理器接收到地址时将翻译的地址提供给存储器。一个逻辑电路响应一个写入信号，自动递增翻译的地址，并响应一个控制信号返回到翻译的地址。连接到逻辑电路的控制电路响应于读取信号以将控制信号提供给逻辑电路。

5. 发明授权

US5269021A Multiprocessor software interface for a graphics processor subsystem employing partially linked dynamic load modules which are downloaded and fully linked at run time 失效
标题翻译：使用部分链接的动态加载模块的图形处理器子系统的多处理器软件接口，这些模块在运行时被下载并完全链接
公开(公告)号：US5269021A
公开(公告)日：1993-12-07
申请号：US420409
申请日：1989-10-12
申请人： Michael A. Denio , William S. Egr , Douglas C. Crawford , Michael D. Asal , Graham Short , James G. Littleton , Jerry R. Van Aken
发明人： Michael A. Denio , William S. Egr , Douglas C. Crawford , Michael D. Asal , Graham Short , James G. Littleton , Jerry R. Van Aken
IPC分类号： G06F9/40 , G06F9/445 , G06F15/16
CPC分类号： G06F9/4425 , G06F9/44521
摘要： An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.
摘要翻译：一种与多处理器计算机系统一起使用的接口，具有主处理器系统和图形处理器系统。该接口允许在主机系统或另一个系统上开发扩展功能，并随后加载到图形处理器系统。该接口包括驻留在主机系统侧和图形系统侧的软件，其在运行时操作以允许从主机上运行的主程序调用该功能。该函数的参数传递给图形系统，以使该函数由图形处理器执行。

6. 发明授权

US5638424A Telephone voice mail delivery system 失效
标题翻译：电话语音邮件传送系统
公开(公告)号：US5638424A
公开(公告)日：1997-06-10
申请号：US610079
申请日：1996-02-29
申请人： Michael A. Denio , James G. Littleton
发明人： Michael A. Denio , James G. Littleton
IPC分类号： H04M1/65 , H04M3/533 , H04M1/64
CPC分类号： H04M1/6505 , H04M3/533
摘要： Apparatus and a method are disclosed for establishing communication between a sending system and a receiving system. Upon initiation of the communication, the sending system sequentially monitors the receiving system for a response from one of a human interface, a non-cooperating system or a cooperating system. If a response from a human interface within the receiving system is received by the sending system, the sending system transmits a message to a human. If a response is not received from a human interface but is received from a non-cooperating system within the receiving system, the sending system transmits a message to an answering machine. If a response is not received from a human interface or a non-cooperating system, but is received from a cooperating system within the receiving system, information is exchanged between the sending system and the cooperating system in an attempt to establish communication.
摘要翻译：公开了用于建立发送系统和接收系统之间的通信的装置和方法。在通信开始时，发送系统从人机接口，非协作系统或协作系统之一顺序地监视接收系统的响应。如果发送系统接收到来自接收系统内的人机接口的响应，则发送系统向人发送消息。如果没有从人机界面接收到响应，但是从接收系统内的非协作系统接收到响应，则发送系统向应答机发送消息。如果没有从人机接口或非协作系统接收到响应，但是从接收系统内的协作系统接收到响应，则在发送系统和协作系统之间交换信息以试图建立通信。

7. 发明授权

US5636335A Graphics computer system having a second palette shadowing data in a first palette 失效
标题翻译：图形计算机系统具有在第一调色板中的第二调色板阴影数据
公开(公告)号：US5636335A
公开(公告)日：1997-06-03
申请号：US479478
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06T15/60
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory. The second palette is connected to the graphics processor permitting it to specify the color data words stored in the second look-up table memory. An interface circuit connects to the host data bus, the host address bus and the second palette. The interface circuit writes data received from the host data bus into the second palette upon detecting predetermined addresses on the host address bus. This causes at least a portion of the second palette to store identical data as stored in corresponding locations of the first palette.
摘要翻译：包括主计算机和图形处理器的图形计算机系统。主机具有主机数据总线和主机地址总线。第一视频存储器存储与显示相对应的颜色代码。第一个视频存储器连接到主机，允许它指定颜色代码。连接到第一视频存储器的第一调色板具有第一查找表存储器，用于调用与从第一视频存储器接收的彩色代码相对应的彩色数据字。第一调色板连接到主计算机，允许其指定存储在第一查找表存储器中的颜色数据字。图形处理器具有本地数据总线和本地地址总线。第二视频存储器存储与显示相对应的颜色代码，图形处理器指定存储在第二视频存储器中的颜色代码。连接到第二视频存储器的第二调色板具有第二查找表存储器。第二调色板连接到图形处理器，允许其指定存储在第二查找表存储器中的颜色数据字。接口电路连接到主机数据总线，主机地址总线和第二个调色板。接口电路在检测到主机地址总线上的预定地址时，将从主机数据总线接收的数据写入第二调色板。这导致第二调色板的至少一部分存储与存储在第一调色板的相应位置中相同的数据。

8. 发明授权

US5355485A First processor for dividing long argument data into packets and storing total packet count and packets in shared buffer for subsequent execution by second processor 失效
标题翻译：第一个处理器用于将长参数数据分成数据包，并将总数据包数和数据包存储在共享缓冲区中，以供后续处理器执行
公开(公告)号：US5355485A
公开(公告)日：1994-10-11
申请号：US25901
申请日：1993-03-03
申请人： Michael A. Denio , James G. Littleton
发明人： Michael A. Denio , James G. Littleton
IPC分类号： G06F15/16 , G06F9/38 , G06F9/42 , G06F9/54 , G06F15/17 , G06F15/177 , G06F13/00
CPC分类号： G06F9/3879 , G06F15/17 , G06F9/4426
摘要： A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. The function may have an argument that requires a large amount of argument data. Each extended function is associated with a special entry point command, which is in turn, associated with a communications routine that handles the transfer of the large argument data from the first processor to the second processor in bursts.
摘要翻译：提供了一种用于将扩展功能添加到多处理器系统的方法，具体地，可以从在第一处理器上运行并由第二处理器执行的编程调用的函数。该函数可能有一个需要大量参数数据的参数。每个扩展功能都与一个特殊的入口点命令相关联，特殊的入口点命令又与处理从第一个处理器到第二个处理器的突发传送大型参数数据的通信程序相关联。

9. 发明授权

US06189077B1 Two computer access circuit using address translation into common register file 失效
标题翻译：两个计算机访问电路使用地址转换为通用寄存器文件
公开(公告)号：US06189077B1
公开(公告)日：2001-02-13
申请号：US08476786
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F1200
CPC分类号： G06F9/30101 , G06F3/14 , G06F3/1438 , G06F9/3879 , G06F12/0284 , G09G5/001 , G09G5/06 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126
摘要： An access circuit for data swapping between two computers and a computer system including the access circuit. Each computer including an address bus for supplying addresses and a data bus for transferring data. The access circuit includes a register file and two address decoder circuits. The register file has a plurality of storage locations for storing data. The register file has dual data ports capable of simultaneous data transfer via the first data port with a first data storage location and via the second data port with a second, different storage location. Each address decoder is connected to the address bus of a corresponding computer and the register file. The address decoders translate an address received on the address bus to a storage location of the register file. Two handshakes circuits are connected to respective address decoders and digital computers. The first and second address decoders are connected to each other. When the storage location of the first address decoder equals the storage location of the second address decoder, one of the handshake circuits signals the corresponding digital computer a memory waitstate or memory fault. At least one of the decoders is be programmable to position in the address space of the corresponding computer. At least one the address decoders includes an autoincrement circuit advances the accessed storage location within the register file to a next storage location upon each data transfer.
摘要翻译：一种用于两个计算机之间的数据交换的访问电路和包括该访问电路的计算机系统。每个计算机包括用于提供地址的地址总线和用于传送数据的数据总线。访问电路包括寄存器文件和两个地址解码器电路。寄存器文件具有用于存储数据的多个存储位置。寄存器文件具有双数据端口，能够经由具有第一数据存储位置的第一数据端口并经由具有第二不同存储位置的第二数据端口同时进行数据传输。每个地址解码器连接到相应计算机的地址总线和寄存器文件。地址解码器将地址总线上接收的地址转换为寄存器文件的存储位置。两个握手电路连接到相应的地址解码器和数字计算机。第一和第二地址解码器彼此连接。当第一地址解码器的存储位置等于第二地址解码器的存储位置时，其中一个握手电路向对应的数字计算机发送一个存储器状态或存储器故障信号。至少一个解码器可编程为位于相应计算机的地址空间中。至少一个地址解码器包括自动增量电路，在每次数据传送时，将所访问的寄存器文件中的存储位置提前到下一个存储位置。

10. 发明授权

US5696923A Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register 失效
标题翻译：图形处理器在写入控制寄存器的同时写入预定地址的影子寄存器
公开(公告)号：US5696923A
公开(公告)日：1997-12-09
申请号：US474863
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G06F9/30 , G06F12/02 , G09G5/06 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/395 , G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F9/30101 , G06F12/0284 , G06F3/14 , G06F3/1438 , G06F9/3879 , G09G5/06 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.
摘要翻译：计算机图形系统包括主计算机和图形处理器。图形处理器包括一个控制寄存器。当图形处理器向控制寄存器写入时，它同时在本地地址总线上产生一个预定的地址，并将数据提供给与写入控制寄存器的数据相同的本地数据总线上。连接到主计算机和图形处理器的影子寄存器电路包括影子寄存器和第一和第二地址解码器。第一地址解码器能够在检测到预定地址时从本地数据总线写入影子寄存器。当检测到主机地址总线上的预定地址时，第二地址解码器能够经由主机数据总线从影子寄存器读取。影子寄存器可选地包括多个比特的消息和多个比特的消息，第一和第二地址解码器使能主机计算机和图形处理器之间的消息传递。影子寄存器电路可选地包括主机中断位和缓冲电路。如果图形处理器产生主机中断信号或影子寄存器的主机中断位具有预定状态，则缓冲电路向主计算机产生主机中断信号。

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