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1. 发明授权

US5627568A Display buffer using minimum number of VRAMs 失效
标题翻译：显示缓冲区使用最小数量的VRAM
公开(公告)号：US5627568A
公开(公告)日：1997-05-06
申请号：US990971
申请日：1992-12-15
申请人： Ian J. Sherlock , Richard D. Simpson , Michael D. Asal
发明人： Ian J. Sherlock , Richard D. Simpson , Michael D. Asal
IPC分类号： G09G5/36 , G09G5/39 , G09G5/00
CPC分类号： G09G5/39 , G09G5/363
摘要： A display buffer includes a plurality of memory banks, each said bank having a plurality of ordered rows of data storage locations. Circuitry controls the storage of a plurality of sequenced lines of display data in said display buffer. A first set of lines of display data is stored at contiguous locations in a first memory bank with the first word of a first line being stored in a location offset from the first location of the first row so a last word of a last line is stored in the last location of the last row. A second set of lines is stored at contiguous locations starting at the first row of the second memory bank. A last line of the second set of lines is stored so that the last word of this last line is stored in the last location of a selected row of the second bank. A third set of lines is stored in a third memory bank starting at a memory line other than the first memory line. If additional space is needed, the display lines wrap around to the first location of the first line of the third bank of memories. A graphics processor may provide the memory addressing and bank selection logic.
摘要翻译：显示缓冲器包括多个存储体，每个所述存储体具有多个排列的数据存储位置行。电路控制在所述显示缓冲器中存储多条排序的显示数据行。第一组显示数据被存储在第一存储体中的连续位置处，其中第一行的第一个字被存储在偏离第一行的第一位置的位置中，从而最后一行的最后一个字被存储在最后一行的最后一个位置。第二组线路存储在从第二存储器组的第一行开始的连续位置处。存储第二组行的最后一行，使得最后一行的最后一个字被存储在第二组的所选行的最后位置。第三组线路存储在从第一存储器线以外的存储线开始的第三存储体中。如果需要额外的空间，则显示线缠绕到第三组存储器的第一行的第一位置。图形处理器可以提供存储器寻址和存储体选择逻辑。

2. 发明授权

US5233690A Video graphics display memory swizzle logic and expansion circuit and method 失效
标题翻译：视频图形显示内存swizzle逻辑和扩展电路和方法
公开(公告)号：US5233690A
公开(公告)日：1993-08-03
申请号：US387568
申请日：1989-07-28
申请人： Ian J. Sherlock , Richard D. Simpson
发明人： Ian J. Sherlock , Richard D. Simpson
IPC分类号： G09G5/393
CPC分类号： G09G5/393
摘要： A circuit controls the reordering of data as it is transferred to control a memory. The data to be reordered is presented such that the ordinate bit position within a data word is uniquely associated with a particular input to a data bus. The bus inputs, however, are connected to the VRAM in an arrangement contrary to the desired ordinate association with the compressed data word. A single swizzle logic circuit operates to allow graphic compressed data to be reordered for presentation to the block-write inputs of a VRAM regardless of the VRAM or pixel size. The circuit relies upon properly expanding the compressed data prior to the actual reordering of the ordinate positions of the data bits. A method for controlling the reordering of data also is described.
摘要翻译：电路控制数据的重新排序，因为它被传送以控制存储器。呈现要重新排序的数据，使得数据字中的纵坐标位置与数据总线的特定输入唯一地相关联。然而，总线输入以与压缩数据字的期望的纵坐标相关联的布置连接到VRAM。单个旋转逻辑电路用于允许图形压缩数据被重排序以呈现给VRAM的块写入输入，而不管VRAM或像素尺寸如何。电路依赖于在数据位的纵坐标位置的实际重新排序之前适当地扩展压缩数据。还描述了一种用于控制数据重新排序的方法。

3. 发明授权

US07016402B2 Digital subscriber line modem with automated line connection 有权
标题翻译：具有自动线路连接的数字用户线路调制解调器
公开(公告)号：US07016402B2
公开(公告)日：2006-03-21
申请号：US09919429
申请日：2001-07-31
申请人： Ian J. Sherlock
发明人： Ian J. Sherlock
IPC分类号： H04B1/38
CPC分类号： H04M11/062
摘要： A DSL modem (50). The DSL modem includes a connector (62) comprising a first pair of conductors (IP1, IP2) and a second pair of conductors (OP1, OP2). The DSL modem further includes both circuitry for transmitting according to a DSL protocol (52) and circuitry for receiving according to a DSL protocol (52). Still further, the DSL modem includes switching circuitry (60) operable to selectively switch to a first position to couple the circuitry for transmitting and the circuitry for receiving to the first pair of conductors and to a second position to couple the circuitry for transmitting and the circuitry for receiving to the second pair of conductors. Lastly, the DSL modem includes circuitry (52, CONTROL) for controlling the switching circuitry to switch to one of the first position and the second position and for then detecting whether DSL service exists along the pair of conductors to which the circuitry for transmitting and the circuitry for receiving is then coupled.
摘要翻译： DSL调制解调器（50）。 DSL调制解调器包括连接器（62），该连接器包括第一对导体（IP 1，IP 2 2）和第二对导体（OP＆lt; 1＆gt; 2＆ SUB>，OP 2）。 DSL调制解调器还包括根据DSL协议（52）发送的电路和用于根据DSL协议（52）接收的电路。此外，DSL调制解调器包括切换电路（60），其可操作以选择性地切换到第一位置以将用于传输的电路和用于接收的电路耦合到第一对导体，以及耦合到用于传输的电路和第二位置用于接收到第二对导体的电路。最后，DSL调制解调器包括用于控制切换电路切换到第一位置和第二位置中的一个的电路（52，CONTROL），然后检测DSL服务是否存在于沿着传输电路的一对导体和然后连接用于接收的电路。

4. 发明授权

US07039017B2 System and method for detecting and locating interferers in a wireless communication system 有权
公开(公告)号：US07039017B2
公开(公告)日：2006-05-02
申请号：US10033006
申请日：2001-12-28
申请人： Ian J. Sherlock
发明人： Ian J. Sherlock
IPC分类号： H04J1/16 , H04Q7/24
CPC分类号： H04W24/00
摘要： A system and method is provided for monitoring interference in a wireless communication system. The system and method monitor error statistic data at one or more devices in a wireless communication system. The error statistic data can be utilized to determine the location of the interference. If any unusual error statistic data is present at the one or more of the devices, raw unprocessed data is provided from the devices experiencing unusual error activity. The raw unprocessed data can be utilized to characterize the interference. For example, the raw unprocessed data can be compared to one or more interference templates to determine an interference type. The raw unprocessed data can be compared between devices in the wireless communication system to determine the location of the interference with increased precision.

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