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1. 发明授权

US5546553A Multifunctional access devices, systems and methods 失效
公开(公告)号：US5546553A
公开(公告)日：1996-08-13
申请号：US359324
申请日：1994-12-15
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/00
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

2. 发明授权

US5636335A Graphics computer system having a second palette shadowing data in a first palette 失效
标题翻译：图形计算机系统具有在第一调色板中的第二调色板阴影数据
公开(公告)号：US5636335A
公开(公告)日：1997-06-03
申请号：US479478
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06T15/60
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory. The second palette is connected to the graphics processor permitting it to specify the color data words stored in the second look-up table memory. An interface circuit connects to the host data bus, the host address bus and the second palette. The interface circuit writes data received from the host data bus into the second palette upon detecting predetermined addresses on the host address bus. This causes at least a portion of the second palette to store identical data as stored in corresponding locations of the first palette.
摘要翻译：包括主计算机和图形处理器的图形计算机系统。主机具有主机数据总线和主机地址总线。第一视频存储器存储与显示相对应的颜色代码。第一个视频存储器连接到主机，允许它指定颜色代码。连接到第一视频存储器的第一调色板具有第一查找表存储器，用于调用与从第一视频存储器接收的彩色代码相对应的彩色数据字。第一调色板连接到主计算机，允许其指定存储在第一查找表存储器中的颜色数据字。图形处理器具有本地数据总线和本地地址总线。第二视频存储器存储与显示相对应的颜色代码，图形处理器指定存储在第二视频存储器中的颜色代码。连接到第二视频存储器的第二调色板具有第二查找表存储器。第二调色板连接到图形处理器，允许其指定存储在第二查找表存储器中的颜色数据字。接口电路连接到主机数据总线，主机地址总线和第二个调色板。接口电路在检测到主机地址总线上的预定地址时，将从主机数据总线接收的数据写入第二调色板。这导致第二调色板的至少一部分存储与存储在第一调色板的相应位置中相同的数据。

3. 发明授权

US5341470A Computer graphics systems, palette devices and methods for shift clock pulse insertion during blanking 失效
标题翻译：计算机图形系统，调色板设备和消隐时移位时钟脉冲插入的方法
公开(公告)号：US5341470A
公开(公告)日：1994-08-23
申请号：US544779
申请日：1990-06-27
申请人： Richard D. Simpson , Jeffrey L. Nye , Michael D. Asal
发明人： Richard D. Simpson , Jeffrey L. Nye , Michael D. Asal
IPC分类号： G09G5/02 , G09G5/06 , G09G5/12 , G09G5/36 , G09G5/39 , G06F15/62
CPC分类号： G09G5/12 , G09G5/06 , G09G5/363 , G09G5/39 , G09G2330/12 , G09G2360/123 , G09G5/022
摘要： A computer graphics system. The system includes a video memory having a shift register adapted for split shift register transfers, and digital computer for controlling the video memory and having a tap point counter clocked by a shift clock signal and also having a blanking circuit with a blanking output. Further, logic circuitry enabled by the blanking output is connected to initiate an extra shift clock pulse for the tap point counter during a blanking interval. Other systems, palette devices, and methods are also disclosed.
摘要翻译：计算机图形系统。该系统包括具有适用于分离移位寄存器传输的移位寄存器的视频存储器，以及用于控制视频存储器并具有由移位时钟信号计时的分接点计数器的数字计算机，并且还具有带有消隐输出的消隐电路。此外，由消隐输出使能的逻辑电路被连接以在消隐间隔期间启动分接点计数器的额外移位时钟脉冲。还公开了其他系统，调色板装置和方法。

4. 发明授权

US6154824A Multifunctional access devices, systems and methods 失效
标题翻译：多功能接入设备，系统和方法
公开(公告)号：US6154824A
公开(公告)日：2000-11-28
申请号：US474866
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/00
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.
摘要翻译：一种用于第一和第二数字计算机的多功能存取电路，每个数字计算机具有用于提供地址的地址总线和用于提供数据的数据总线。访问电路具有地址解码器，其具有用于来自第一计算机的地址总线的输入，以及地址转换器电路，其具有用于由第一计算机的地址总线提供的地址的地址输入，并将翻译的地址输出到第二计算机的地址总线。地址转换器电路还具有可由地址解码器和数据输入端选择的寄存器，用来从第一台计算机的数据总线的数据对所选择的寄存器进行编程。在访问电路中还有一个端口电路，具有由地址解码器控制的寄存器，用于从第一计算机的数据总线输入地址信息，并在第二计算机的地址总线上断言地址信息。此外，模式控制电路连接到地址解码器并连接到数据总线以对模式控制电路进行编程，以选择性地建立地址转换器电路和端口电路的操作。还描述了其他访问电路，设备，系统和方法。

5. 发明授权

US5696924A Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads 失效
标题翻译：具有地址转换的存储器访问电路在写入时执行翻译地址的自动增量，并在读取时返回到翻译的地址
公开(公告)号：US5696924A
公开(公告)日：1997-12-09
申请号：US487750
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G09G1/16 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G06F12/10
CPC分类号： G06F3/1438 , G06F3/14 , G09G5/06 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.
摘要翻译：一种与具有地址总线，数据总线和一组控制线的图形处理器一起使用的存储器存取系统。连接到图形处理器的地址总线的地址转换器电路在从图形处理器接收到地址时将翻译的地址提供给存储器。一个逻辑电路响应一个写入信号，自动递增翻译的地址，并响应一个控制信号返回到翻译的地址。连接到逻辑电路的控制电路响应于读取信号以将控制信号提供给逻辑电路。

6. 发明授权

US06189077B1 Two computer access circuit using address translation into common register file 失效
标题翻译：两个计算机访问电路使用地址转换为通用寄存器文件
公开(公告)号：US06189077B1
公开(公告)日：2001-02-13
申请号：US08476786
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F1200
CPC分类号： G06F9/30101 , G06F3/14 , G06F3/1438 , G06F9/3879 , G06F12/0284 , G09G5/001 , G09G5/06 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126
摘要： An access circuit for data swapping between two computers and a computer system including the access circuit. Each computer including an address bus for supplying addresses and a data bus for transferring data. The access circuit includes a register file and two address decoder circuits. The register file has a plurality of storage locations for storing data. The register file has dual data ports capable of simultaneous data transfer via the first data port with a first data storage location and via the second data port with a second, different storage location. Each address decoder is connected to the address bus of a corresponding computer and the register file. The address decoders translate an address received on the address bus to a storage location of the register file. Two handshakes circuits are connected to respective address decoders and digital computers. The first and second address decoders are connected to each other. When the storage location of the first address decoder equals the storage location of the second address decoder, one of the handshake circuits signals the corresponding digital computer a memory waitstate or memory fault. At least one of the decoders is be programmable to position in the address space of the corresponding computer. At least one the address decoders includes an autoincrement circuit advances the accessed storage location within the register file to a next storage location upon each data transfer.
摘要翻译：一种用于两个计算机之间的数据交换的访问电路和包括该访问电路的计算机系统。每个计算机包括用于提供地址的地址总线和用于传送数据的数据总线。访问电路包括寄存器文件和两个地址解码器电路。寄存器文件具有用于存储数据的多个存储位置。寄存器文件具有双数据端口，能够经由具有第一数据存储位置的第一数据端口并经由具有第二不同存储位置的第二数据端口同时进行数据传输。每个地址解码器连接到相应计算机的地址总线和寄存器文件。地址解码器将地址总线上接收的地址转换为寄存器文件的存储位置。两个握手电路连接到相应的地址解码器和数字计算机。第一和第二地址解码器彼此连接。当第一地址解码器的存储位置等于第二地址解码器的存储位置时，其中一个握手电路向对应的数字计算机发送一个存储器状态或存储器故障信号。至少一个解码器可编程为位于相应计算机的地址空间中。至少一个地址解码器包括自动增量电路，在每次数据传送时，将所访问的寄存器文件中的存储位置提前到下一个存储位置。

7. 发明授权

US5696923A Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register 失效
标题翻译：图形处理器在写入控制寄存器的同时写入预定地址的影子寄存器
公开(公告)号：US5696923A
公开(公告)日：1997-12-09
申请号：US474863
申请日：1995-06-07
申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
发明人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
IPC分类号： G06F3/14 , G06F9/30 , G06F12/02 , G09G5/06 , G09G5/14 , G09G5/36 , G09G5/39 , G09G5/395 , G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F9/30101 , G06F12/0284 , G06F3/14 , G06F3/1438 , G06F9/3879 , G09G5/06 , G09G5/14 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/126 , G09G5/001
摘要： A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.
摘要翻译：计算机图形系统包括主计算机和图形处理器。图形处理器包括一个控制寄存器。当图形处理器向控制寄存器写入时，它同时在本地地址总线上产生一个预定的地址，并将数据提供给与写入控制寄存器的数据相同的本地数据总线上。连接到主计算机和图形处理器的影子寄存器电路包括影子寄存器和第一和第二地址解码器。第一地址解码器能够在检测到预定地址时从本地数据总线写入影子寄存器。当检测到主机地址总线上的预定地址时，第二地址解码器能够经由主机数据总线从影子寄存器读取。影子寄存器可选地包括多个比特的消息和多个比特的消息，第一和第二地址解码器使能主机计算机和图形处理器之间的消息传递。影子寄存器电路可选地包括主机中断位和缓冲电路。如果图形处理器产生主机中断信号或影子寄存器的主机中断位具有预定状态，则缓冲电路向主计算机产生主机中断信号。

8. 发明授权

US5627568A Display buffer using minimum number of VRAMs 失效
标题翻译：显示缓冲区使用最小数量的VRAM
公开(公告)号：US5627568A
公开(公告)日：1997-05-06
申请号：US990971
申请日：1992-12-15
申请人： Ian J. Sherlock , Richard D. Simpson , Michael D. Asal
发明人： Ian J. Sherlock , Richard D. Simpson , Michael D. Asal
IPC分类号： G09G5/36 , G09G5/39 , G09G5/00
CPC分类号： G09G5/39 , G09G5/363
摘要： A display buffer includes a plurality of memory banks, each said bank having a plurality of ordered rows of data storage locations. Circuitry controls the storage of a plurality of sequenced lines of display data in said display buffer. A first set of lines of display data is stored at contiguous locations in a first memory bank with the first word of a first line being stored in a location offset from the first location of the first row so a last word of a last line is stored in the last location of the last row. A second set of lines is stored at contiguous locations starting at the first row of the second memory bank. A last line of the second set of lines is stored so that the last word of this last line is stored in the last location of a selected row of the second bank. A third set of lines is stored in a third memory bank starting at a memory line other than the first memory line. If additional space is needed, the display lines wrap around to the first location of the first line of the third bank of memories. A graphics processor may provide the memory addressing and bank selection logic.
摘要翻译：显示缓冲器包括多个存储体，每个所述存储体具有多个排列的数据存储位置行。电路控制在所述显示缓冲器中存储多条排序的显示数据行。第一组显示数据被存储在第一存储体中的连续位置处，其中第一行的第一个字被存储在偏离第一行的第一位置的位置中，从而最后一行的最后一个字被存储在最后一行的最后一个位置。第二组线路存储在从第二存储器组的第一行开始的连续位置处。存储第二组行的最后一行，使得最后一行的最后一个字被存储在第二组的所选行的最后位置。第三组线路存储在从第一存储器线以外的存储线开始的第三存储体中。如果需要额外的空间，则显示线缠绕到第三组存储器的第一行的第一位置。图形处理器可以提供存储器寻址和存储体选择逻辑。

9. 发明授权

US4849920A Apparatus for locating and representing the position of an end "1" bit of a number in a multi-bit number format 失效
标题翻译：用于定位和表示多位数字格式的数字的结尾“1”位的位置的装置
公开(公告)号：US4849920A
公开(公告)日：1989-07-18
申请号：US839004
申请日：1986-03-12
申请人： Richard D. Simpson , Michael D. Asal
发明人： Richard D. Simpson , Michael D. Asal
IPC分类号： G06F7/00 , G06F7/74 , G06F7/76 , H03M7/00
CPC分类号： G06F7/74
摘要： The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group. The units are coupled together so that a representation from a preceding unit blocks the output of a representation from a subsequent unit.
摘要翻译：通过将反相位并行地并入到各个或非门（61至68）的输入端来检测输入号码中的“1”位的位置，其另一个输入端连接到动态域链的节点效应晶体管（A1至A8），沿着该晶体管传播“O”。两个O在NOR门的输入端的重合使得它产生一个“1”输出，表示输入号码的结尾“1”的位置。 NOR门（L1〜L8）的输出端连接到场效应晶体管阵列（LA）的列导体，该场效应晶体管阵列（LA）在行导体阵列上平行生成，反相，二进制编码形成对应于NOR 门产生“1”输出。该装置可以响应于输入号码的相邻组的每一组而分成若干单元（U1至U4），每个单元产生其组中的端“1”的位置的表示。这些单元耦合在一起，使得来自前一单元的表示阻止来自后续单元的表示的输出。

10. 发明授权

US07642938B2 Gray code to sign and magnitude converter 有权
标题翻译：格雷码为符号和幅度转换器
公开(公告)号：US07642938B2
公开(公告)日：2010-01-05
申请号：US12028469
申请日：2008-02-08
申请人： Richard D. Simpson
发明人： Richard D. Simpson
IPC分类号： H03M7/04
CPC分类号： H03M7/16 , H03M7/165
摘要： The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.
摘要翻译：本发明涉及格雷码及其转换为符号和幅度表示。格雷码用于闪存ADC（模数转换器），将模拟波形转换为采样二进制值。这可以通过温度计代码来实现，并且本发明解决了由于不确定的温度计代码值导致的误差传播的问题。特别地，本发明提供了一种格雷码，用于符号和幅度转换器，其被布置为产生除了符号位之外的其输出的比特，对于格雷码的相同代码，其与来自符号位改变值的边界相同的距离格雷码按照它们的价值排列。

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