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1. 发明授权

US07500043B2 Array of data processing elements with variable precision interconnect 有权
标题翻译：具有可变精度互连的数据处理元件阵列
公开(公告)号：US07500043B2
公开(公告)日：2009-03-03
申请号：US11379666
申请日：2006-04-21
申请人： Paul B. Wood
发明人： Paul B. Wood
IPC分类号： G06F13/14 , G06F13/36 , G06F13/40 , G06F1/12 , H04J15/00 , H04J3/06
CPC分类号： G06F15/8007 , H03K19/17728 , H03K19/17736 , H03K19/1774
摘要： Systems and methods for processing data using an array of data processing elements that are coupled together with a variable precision interconnect. One embodiment comprises data processing elements coupled by variable precision interconnects to form a row-column array. The interconnects and/or data processing elements may be synchronous or asynchronous. The data processing elements may operate in a fixed manner, or they may be programmable, and selectable data processing elements in the array may be bypassed. The interconnects and data processing elements may be configured to handle data in a digit-serial manner, with tags for each digit identifying whether the digit is the first and/or last digit in a data word. The data processing elements may be coupled to a system bus that enables communication of data between the data processing elements and external devices and allows control information to be communicated to and from the data processing elements.
摘要翻译：使用与可变精密互连耦合在一起的数据处理元件阵列来处理数据的系统和方法。一个实施例包括通过可变精密互连耦合以形成行列阵列的数据处理元件。互连和/或数据处理元件可以是同步的或异步的。数据处理元件可以以固定的方式操作，或者它们可以是可编程的，并且可以绕过阵列中的可选数据处理元件。互连和数据处理元件可以被配置为以数字串行方式处理数据，每个数字的标签识别数字是数据字中的第一个和/或最后一个数字。数据处理元件可以耦合到能够在数据处理元件和外部设备之间进行数据通信的系统总线，并允许将控制信息传送到数据处理元件和从数据处理元件传送。

2. 发明授权

US5613053A Video graphics controller with automatic starting for line draws 失效
标题翻译：视频图形控制器，自动启动线绘制
公开(公告)号：US5613053A
公开(公告)日：1997-03-18
申请号：US823529
申请日：1992-01-21
申请人： Thomas M. Albers , John V. Eberst , Darwin Fontenot , Richard L. Pyra , Mark W. Welker , Paul B. Wood , Jack E. Bresenham
发明人： Thomas M. Albers , John V. Eberst , Darwin Fontenot , Richard L. Pyra , Mark W. Welker , Paul B. Wood , Jack E. Bresenham
IPC分类号： G06T11/20 , G06T11/00
CPC分类号： G06T11/203
摘要： A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.
摘要翻译：图形处理器使用线绘制工具来接收指示线的相应第一和第二端点的坐标的第一和第二值。第二值的接收由线条绘制设备感测，并且响应于对第二值的感测产生线数据。

3. 发明授权

US5291187A High-speed video display system 失效
标题翻译：高速视频显示系统
公开(公告)号：US5291187A
公开(公告)日：1994-03-01
申请号：US695963
申请日：1991-05-06
申请人： Paul B. Wood , Brian F. Bounds
发明人： Paul B. Wood , Brian F. Bounds
IPC分类号： G09G5/06 , G09G5/08 , G09G5/395 , G09G1/02
CPC分类号： G09G5/395 , G09G5/06 , G09G5/08
摘要： A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. As a result, the pixel clock rate is not dependent by the propagation delay of the output clock signal through the video controller, and higher speed system operation is achieved.
摘要翻译：公开了包括视频数模转换器的图形子系统。高速振荡器以要显示像素的频率产生像素时钟信号。包括在视频DAC中的分频器是一个分频器，它提供一个输出时钟信号，该输出时钟信号的周期是像素时钟信号的倍数，该倍数对应于由视频DAC提供的像素数据的复用电平; 这个多重可以相等的统一。系统中的视频控制器接收输出时钟信号，并产生时钟信号以控制帧存储器的串行端口，并且还控制视频DAC中第一级的锁存。视频DAC中的第一级锁存器锁存来自帧存储器的多个像素数据，并且视频DAC中的多路复用器将数据呈现为彩色调色板RAM或彩色非多路复用模式下的调色板RAM周围，根据像素时钟信号。结果，像素时钟速率不依赖于通过视频控制器的输出时钟信号的传播延迟，并且实现更高速度的系统操作。

4. 发明授权

US07536535B2 Self-timed processor 失效
标题翻译：自定时处理器
公开(公告)号：US07536535B2
公开(公告)日：2009-05-19
申请号：US11379681
申请日：2006-04-21
申请人： Paul B. Wood
发明人： Paul B. Wood
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/30181 , G06F9/3869 , G06F9/3871
摘要： Systems and methods for executing program instructions in a data processor at a variable rate. In one embodiment, a processor is configured to examine received instructions, identify an execution time associated with each instruction, and generate clock pulses at necessary intervals to obtain the appropriate execution time for each instruction. Instructions may be associated with types or “bins” that are in turn associated with corresponding execution times. The clock pulses may be generated by routing successive pulses through circuits that delay the pulses by desired amounts of time. The processor may also be configured to identify instructions which are input/output (I/O) instructions and are initiated or terminated by completion of handshake procedures and therefore have execution times that vary from one instance to the next.
摘要翻译：用于以可变速率执行数据处理器中的程序指令的系统和方法。在一个实施例中，处理器被配置为检查接收到的指令，识别与每个指令相关联的执行时间，并且以必要的间隔生成时钟脉冲以获得每个指令的适当执行时间。指令可能与相应的执行时间相关联的类型或“仓”相关联。时钟脉冲可以通过将连续的脉冲路由到将脉冲延迟期望的时间量的电路来产生。处理器还可以被配置为识别作为输入/输出（I / O）指令的指令，并且通过完成握手过程来启动或终止指令，因此具有从一个实例到下一个实例的执行时间。

5. 发明授权

US5974478A System for command processing or emulation in a computer system, such as emulation of DMA commands using burst mode data transfer for sound 失效
标题翻译：用于计算机系统中的命令处理或仿真的系统，例如使用突发模式数据传输的DMA命令的仿真
公开(公告)号：US5974478A
公开(公告)日：1999-10-26
申请号：US888910
申请日：1997-07-07
申请人： Paul B. Wood , Marc M. Stimak
发明人： Paul B. Wood , Marc M. Stimak
IPC分类号： G06F13/24 , G06F13/28
CPC分类号： G06F13/28
摘要： A system and method for providing sound in a computer are disclosed. An audio module for controlling digitized sound I/O is included in a media stream controller. The media stream controller may also coordinate graphics and video which allows multiple media subsystems to be supported from a single bus device. A software application may initiate sound data transfer by sending a conventional DMA mode command to the media stream controller. The media stream controller activates an audio interrupt service routine which processes the request without using a conventional DMA controller. Digital sound data is transferred across a local bus using high speed burst mode block transfer commands and is buffered by the media stream controller in a display memory. Concurrently, the media stream controller may output sound data from the display memory to a sound output device using a double buffering method. Alternatively, the media stream controller may read sound data from a sound input device and store it in the display memory. The audio interrupt service routine may be activated to transfer the sound data in blocks to a software application. After sound data transfer is complete the audio interrupt service routine may reset the count in the DMA controller to provide compatibility with software applications written for DMA mode transfer. Thus high speed burst mode block transfer may be used with sound data to free up bandwidth for video, graphics and other uses, and yet still provide compatibility with conventional DMA mode sound I/O.
摘要翻译：公开了一种用于在计算机中提供声音的系统和方法。用于控制数字化声音I / O的音频模块被包括在媒体流控制器中。媒体流控制器还可以协调允许从单个总线设备支持多个媒体子系统的图形和视频。软件应用可以通过向媒体流控制器发送常规DMA模式命令来发起声音数据传输。媒体流控制器激活音频中断服务程序，处理请求而不使用常规的DMA控制器。数字声音数据通过使用高速突发模式块传输命令的本地总线传送，并被媒体流控制器在显示存储器中缓冲。同时，媒体流控制器可以使用双缓冲方法将声音数据从显示存储器输出到声音输出设备。或者，媒体流控制器可以从声音输入设备读取声音数据并将其存储在显示存储器中。可以激活音频中断服务程序以将块中的声音数据传送到软件应用程序。在声音数据传输完成后，音频中断服务程序可能会重置DMA控制器中的计数，以提供与为DMA模式传输编写的软件应用程序的兼容性。因此，高速突发模式块传输可以与声音数据一起使用以释放视频，图形和其他用途的带宽，但仍然提供与常规DMA模式声音I / O的兼容性。

6. 发明授权

US5790111A High-speed video display system 失效
公开(公告)号：US5790111A
公开(公告)日：1998-08-04
申请号：US588324
申请日：1996-01-18
申请人： Paul B. Wood , Brian F. Bounds
发明人： Paul B. Wood , Brian F. Bounds
IPC分类号： G09G5/06 , G09G5/08 , G09G5/395 , G09G5/00
CPC分类号： G09G5/395 , G09G5/06 , G09G5/08
摘要： A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. As a result, the pixel clock rate is not dependent by the propagation delay of the output clock signal through the video controller, and higher speed system operation is achieved.

7. 发明授权

US4412294A Display system with multiple scrolling regions 失效
标题翻译：具有多个滚动区域的显示系统
公开(公告)号：US4412294A
公开(公告)日：1983-10-25
申请号：US237316
申请日：1981-02-23
申请人： LaVaughn F. Watts , Ronald L. Smith , Yogendra C. Pandya , Paul B. Wood
发明人： LaVaughn F. Watts , Ronald L. Smith , Yogendra C. Pandya , Paul B. Wood
IPC分类号： G09G1/00 , G09G5/14 , G06F3/14
CPC分类号： G09G5/14 , G09G1/007
摘要： A data display and management system includes a microprocessor whose functions are implemented by instructions in data from a directly connected main memory. A mass data storage memory is connected to the main memory and has permanently stored instructions therein for the microprocessor. A display control system which operates asynchronously with the microprocessor includes a display controller, display memory, character memory means, and a visual character attribute generator. By linking one or more row attribute bytes, or pointers, to each row of characters stored in the display memory the display controller performs character and row manipulation on a display device without transferring whole blocks of data in the display memory. Multi-region display segmentation into horizontal and vertical split regions, smooth or discrete scrolling of individual regions, and various editing functions are achieved by modifying the associated display memory pointers.
摘要翻译：数据显示和管理系统包括微处理器，其功能由来自直接连接的主存储器的数据中的指令实现。大容量数据存储存储器连接到主存储器，并且在其中永久地存储用于微处理器的指令。与微处理器异步操作的显示控制系统包括显示控制器，显示存储器，字符存储器装置和视觉字符属性生成器。通过将一个或多个行属性字节或指针链接到存储在显示存储器中的每行字符，显示控制器在显示设备上执行字符和行操作，而不在显示存储器中传输整个数据块。通过修改相关联的显示存储器指针来实现多区域显示分割成水平和垂直分割区域，单个区域的平滑或离散滚动以及各种编辑功能。

8. 发明授权

US5940610A Using prioritized interrupt callback routines to process different types of multimedia information 失效
标题翻译：使用优先级中断回调例程处理不同类型的多媒体信息
公开(公告)号：US5940610A
公开(公告)日：1999-08-17
申请号：US720891
申请日：1996-10-03
申请人： David C. Baker , Michael D. Asal , Jonathan I. Siann , Paul B. Wood , Jeffrey L. Nye , Stephen G. Glennon , Matthew D. Bates
发明人： David C. Baker , Michael D. Asal , Jonathan I. Siann , Paul B. Wood , Jeffrey L. Nye , Stephen G. Glennon , Matthew D. Bates
IPC分类号： G09G5/02 , G09G5/08 , G09G5/36 , G09G5/395 , H04N5/44 , G06F13/00
CPC分类号： G09G5/363 , G09G5/08 , G09G5/395 , G09G2340/125 , G09G5/02 , H04N5/4401
摘要： Multimedia information (e.g. graphics, video, sound, control information) passes through a system bus from a CPU main memory to a display memory in accordance with CPU commands. The information may be packetized with associated packet types identifying the different media. A media stream controller processes the information and passes the processed information to the display memory. Controllers in the media stream controller individually pass multimedia information to the display memory. A PACDAC controller in the media stream controller causes media (e.g. graphics, video) in the display memory to be transferred to a PACDAC for display. The format, sequence, and rate of this transfer may be flexibly controlled by software on a frame by frame basis. Arbitration logic establishes priorities for the different controllers in the media stream controller so they may share a single bus for accessing the display memory. A single interrupt controller coordinates interrupts (e.g. at a single level) to provide priorities based upon the type of interrupt cause or media. Each interrupt cause activates only the appropriate callback functions. Two different virtual machine sessions (e.g. Windows, DOS) share an interrupt line to process interrupt requests form one (1) session (e.g. Windows) before processing interrupt requests from the other.
摘要翻译：多媒体信息（例如，图形，视频，声音，控制信息）根据CPU命令从CPU主存储器传递到显示存储器。该信息可以用识别不同媒体的相关联的分组类型来分组。媒体流控制器处理信息并将处理的信息传递到显示存储器。媒体流控制器中的控制器将多媒体信息单独传递到显示存储器。媒体流控制器中的PACDAC控制器使显示存储器中的媒体（例如，图形，视频）被传送到PACDAC进行显示。该传输的格式，顺序和速率可以由软件在逐帧的基础上灵活地控制。仲裁逻辑为媒体流控制器中的不同控制器确定优先级，因此它们可以共享用于访问显示存储器的单个总线。单个中断控制器协调中断（例如在单个级别），以根据中断原因或介质的类型提供优先级。每个中断原因仅激活适当的回调函数。在处理来自另一个的中断请求之前，两个不同的虚拟机会话（例如Windows，DOS）共享中断线来处理从一（1）个会话（例如Windows）的中断请求。

9. 发明授权

US5740602A Wire harness assembly system 失效
标题翻译：线束装配系统
公开(公告)号：US5740602A
公开(公告)日：1998-04-21
申请号：US658075
申请日：1996-06-04
申请人： Eric C. Peterson , Alex H. Damalas , Glynn R. Bartlett , Steven B. Farmer , Leslie B. Hoffman , Tak Kameoka , Horace H. Wacaser , Paul B. Wood
发明人： Eric C. Peterson , Alex H. Damalas , Glynn R. Bartlett , Steven B. Farmer , Leslie B. Hoffman , Tak Kameoka , Horace H. Wacaser , Paul B. Wood
IPC分类号： G05B19/418 , H01R43/052 , H01R43/20 , H01R43/28 , H01R43/055
CPC分类号： H01R43/20 , G05B19/41805 , G05B19/4182 , H01R43/052 , H01R43/28 , Y02P90/04 , Y02P90/083 , Y10T29/49153 , Y10T29/49194 , Y10T29/5187 , Y10T29/5193 , Y10T29/53213 , Y10T29/53235 , Y10T29/53239 , Y10T29/53243
摘要： A method and apparatus for making wire harness. The apparatus includes the use of a sequential wire processor that serially and sequentially fabricates circuits having terminal ends. The terminated circuits are transferred by a transfer means to an upstanding carousel provided with arrays of circuit-receiving clips. The transfer means receives terminated circuits from the sequential wire processor and places them on the clips of the carousel. The carousel is then moved to an assembly line and robotic station where robots remove the circuits from the clips of the carousel and place the terminated ends of the circuits in cavities of connectors strategically located on the assembly line. The robots have end effectors that physically insert the terminal ends into the connector cavities.
摘要翻译：一种制造线束的方法和装置。该装置包括使用串行和顺序地制造具有终端的电路的顺序有线处理器。终端电路通过传送装置传送到具有电路接收夹具阵列的直立传送带。转移装置从顺序的线处理器接收终止的电路并将它们放置在转盘的夹子上。然后将转盘移动到装配线和机器人站，其中机器人从圆盘传送带的夹子上移除电路，并将电路的终止端放置在策略性地位于装配线上的连接器的空腔中。机器人具有将终端物理地插入连接器腔中的终端执行器。

10. 发明授权

US5732279A System and method for command processing or emulation in a computer system using interrupts, such as emulation of DMA commands using burst mode data transfer for sound or the like 失效
标题翻译：在使用中断的计算机系统中进行命令处理或仿真的系统和方法，例如使用突发模式数据传输进行声音等的DMA命令的仿真
公开(公告)号：US5732279A
公开(公告)日：1998-03-24
申请号：US337924
申请日：1994-11-10
申请人： Paul B. Wood , Marc M. Stimak
发明人： Paul B. Wood , Marc M. Stimak
IPC分类号： G06F13/24 , G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A system and method for providing sound in a computer are disclosed. An audio module for controlling digitized sound I/O is included in a media stream controller. The media stream controller may also coordinate graphics and video which allows multiple media subsystems to be supported from a single bus device. A software application may initiate sound data transfer by sending a conventional DMA mode command to the media stream controller. The media stream controller activates an audio interrupt service routine which processes the request without using a conventional DMA controller. Digital sound data is transferred across a local bus using high speed burst mode block transfer commands and is buffered by the media stream controller in a display memory. Concurrently, the media stream controller may output sound data from the display memory to a sound output device using a double buffering method. Alternatively, the media stream controller may read sound data from a sound input device and store it in the display memory. The audio interrupt service routine may be activated to transfer the sound data in blocks to a software application. After sound data transfer is complete the audio interrupt service routine may reset the count in the DMA controller to provide compatibility with software applications written for DMA mode transfer, and thereby achieve a form of DMA emulation. Thus high speed burst mode block transfer may be used with sound data to free up bandwidth for video, graphics and other uses, and yet still provide compatibility with conventional DMA mode sound I/O.
摘要翻译：公开了一种用于在计算机中提供声音的系统和方法。用于控制数字化声音I / O的音频模块被包括在媒体流控制器中。媒体流控制器还可以协调允许从单个总线设备支持多个媒体子系统的图形和视频。软件应用可以通过向媒体流控制器发送常规DMA模式命令来发起声音数据传输。媒体流控制器激活音频中断服务程序，处理请求而不使用常规的DMA控制器。数字声音数据通过使用高速突发模式块传输命令的本地总线传送，并被媒体流控制器在显示存储器中缓冲。同时，媒体流控制器可以使用双缓冲方法将声音数据从显示存储器输出到声音输出设备。或者，媒体流控制器可以从声音输入设备读取声音数据并将其存储在显示存储器中。可以激活音频中断服务程序以将块中的声音数据传送到软件应用程序。在声音数据传输完成后，音频中断服务程序可能会重置DMA控制器中的计数，以提供与为DMA模式传输编写的软件应用程序的兼容性，从而实现DMA仿真形式。因此，高速突发模式块传输可以与声音数据一起使用以释放视频，图形和其他用途的带宽，但仍然提供与常规DMA模式声音I / O的兼容性。

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