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1. 发明授权

US4095270A Method of implementing manual operations 失效
标题翻译：执行手册操作的方法
公开(公告)号：US4095270A
公开(公告)日：1978-06-13
申请号：US776576
申请日：1977-03-11
申请人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Guenter Knauft , Stephan Richter , Hermann Schulze-Schoelling
发明人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Guenter Knauft , Stephan Richter , Hermann Schulze-Schoelling
IPC分类号： G06F11/22 , G06F3/023 , G06F9/00 , G06F9/46 , G06F11/36 , G06F9/18
CPC分类号： G06F3/0232
摘要： A method for performing manual operations, such as address compare equal stop, single cycle alter, etc., in a time slice controlled microprocessor with microprogramming, which avoids stopping the processor clock when any of the programs requires a manual operation. This problem is solved by assigning the manual operations to a specific program, which for the other programs in the multiprogram environment executes the manual operations required.

2. 发明授权

US4109311A Instruction execution modification mechanism for time slice controlled data processors 失效
标题翻译：时间控制数据处理器的指令执行修改机制
公开(公告)号：US4109311A
公开(公告)日：1978-08-22
申请号：US725757
申请日：1976-09-23
申请人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Stephan Richter , Helmut Schaal , Hermann Schulze-Schoelling
发明人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Stephan Richter , Helmut Schaal , Hermann Schulze-Schoelling
IPC分类号： G06F12/00 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/318 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/06 , G06F15/16 , G06F15/177 , G06F9/19
CPC分类号： G06F9/4825 , G06F9/226 , G06F9/268 , G06F9/28 , G06F9/3851
摘要： An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions. If, during a given time slice interval, the program to be executed is on the modifiable program list and the instruction to be executed is on the modifiable instruction list and the appropriate condition is occurring in the data processing system, then the modification storage mechanism is enabled to send the modification signals for this instruction to the instruction execution unit for modifying the normal execution of this instruction.

3. 发明授权

US4295220A Clock check circuits using delayed signals 失效
标题翻译：使用延迟信号的时钟检查电路
公开(公告)号：US4295220A
公开(公告)日：1981-10-13
申请号：US98587
申请日：1979-11-29
申请人： Arnold Blum , Hellmuth R. Geng , Hermann Schulze-Schoelling , Bernd Spaeth
发明人： Arnold Blum , Hellmuth R. Geng , Hermann Schulze-Schoelling , Bernd Spaeth
IPC分类号： G01R31/28 , G01R31/3183 , G04D7/00 , H03K5/26 , H04M3/24 , H03K5/19 , G06F1/04
CPC分类号： H04M3/24 , H03K5/26
摘要： In a data processing or transmission system which includes at least two synchronized clocks, for example--T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock.Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
摘要翻译：在包括至少两个同步时钟的数据处理或传输系统中，例如T形环A和B，其产生用于微指令执行的定时脉冲Tai和Tbi，由从时钟接收脉冲的逻辑电路来检查同步。至少一个脉冲被延迟一个或多个脉冲周期持续时间ti。逻辑电路输出信号用作由独立的检查振荡器或时钟周期性地设置的指示器锁存器的输入。在优选实施例中，延迟由主 - 从触发器引入，主 - 从触发器接收T信号的预定组合并由独立检查时钟设置。延迟锁存器和关联的与门可以用于延迟和未延迟T信号的不同逻辑组合。该方案可以轻松扩展，以容纳两个以上的同步操作时钟。这些电路不仅检查时钟的瞬时同步，还检查时钟脉冲的正确排序。如果每个微指令执行的T形环计数器以可变数量的时钟脉冲操作，则该检查也是可行的。

4. 发明授权

US4231085A Arrangement for micro instruction control 失效
标题翻译：微指令控制安排
公开(公告)号：US4231085A
公开(公告)日：1980-10-28
申请号：US934781
申请日：1978-08-18
申请人： Dieter Bazlen , Rolf Berger , Arnold Blum , Dietrich W. Bock , Herbert Chilinski , Hellmuth R. Geng , Johann Hajdu , Fritz Irro , Siegfried Neuber , Udo Wille
发明人： Dieter Bazlen , Rolf Berger , Arnold Blum , Dietrich W. Bock , Herbert Chilinski , Hellmuth R. Geng , Johann Hajdu , Fritz Irro , Siegfried Neuber , Udo Wille
IPC分类号： G06F9/22 , G06F9/12
CPC分类号： G06F9/226
摘要： In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.
摘要翻译：在微控制数据处理系统中，通过使用两个总线路径来将控制信号从微程序控制传送到由这些信号控制的集成电路模块所需的线和引脚的数量被保存，用于将控制信号分配到模块。专用于预解码控制信号功能的第一路径，并且共享用于传送数据和控制信号功能的第二路径。每个受控模块包括用于组合地解码通过两条路径接收的控制信号功能的附加解码电路。

5. 发明授权

US3959638A Highly available computer system 失效
标题翻译：高可用的计算机系统
公开(公告)号：US3959638A
公开(公告)日：1976-05-25
申请号：US547672
申请日：1975-02-06
申请人： Arnold Blum , Fritz Irro , Guenther Sonntag
发明人： Arnold Blum , Fritz Irro , Guenther Sonntag
IPC分类号： G06F11/00 , G06F11/20 , G06F13/14 , G06F15/16 , G06F15/177
CPC分类号： G06F11/20
摘要： For increasing the availability of a modular computer, a control unit and switches are provided, the latter being connected in between the control storages and the remaining identical hardware of the processor. In the case of a hardware error of one processor, its control storage is switched for a specific period of time to the same hardware of another processor which interrupts its own tasks, assuming the tasks of the defective processor for the time during which the control storage of the defective processor remains switched off. Subsequently, the former or non-defective processor resumes its own tasks. The task cycles assigned to one processor or the other can be specified to be identical or as a function of the respective processing requirements.
摘要翻译：为了增加模块化计算机的可用性，提供了控制单元和开关，后者连接在控制存储器和处理器的其余相同的硬件之间。在一个处理器的硬件错误的情况下，其控制存储器在特定的时间段内切换到中断其自己的任务的另一个处理器的同一个硬件，假设在处理时间内该缺陷处理器的任务的缺陷处理器保持关闭。随后，前者或无缺陷处理器恢复自己的任务。分配给一个处理器或另一个处理器的任务循环可以被指定为相同的或者作为相应处理要求的函数。

6. 发明授权

US5164818A Removable VLSI assembly 失效
标题翻译：可拆卸的VLSI总成
公开(公告)号：US5164818A
公开(公告)日：1992-11-17
申请号：US765072
申请日：1991-09-24
申请人： Arnold Blum , Frank Gerth , Manfred Perske , Manfred Schmidt
发明人： Arnold Blum , Frank Gerth , Manfred Perske , Manfred Schmidt
IPC分类号： H01L23/12 , H01L23/48 , H01L23/50 , H01R4/02 , H01R4/24 , H05K1/18 , H05K3/28 , H05K3/30 , H05K3/32 , H05K3/34
CPC分类号： H01L23/48 , H05K3/306 , H05K3/32 , H01L2924/0002 , H05K2201/09472 , H05K2201/10575 , H05K2201/10689 , H05K2201/10704 , H05K2203/0285 , H05K2203/1189 , H05K2203/176 , H05K3/281 , H05K3/3463
摘要： A system for mounting VLSI devices on a substrate is disclosed, offering a high contact density. Each package consists of a semiconductor device having protruding elongated contact pin (2) on its surface and a wiring substrate having a cavity (3) on its surface. The cavities are filed with a conductive material (7) of a low melting point composition and sealed with a thin non-conductive foil (4). During packaging, the contact pins are made to penetrate the foil, and extend into the conductive alloy, thus making electrical contact therewith. To ease the penetration of the foil, the contact pins could be set into oscillating motion by means of an ultrasonic generator.

7. 发明授权

US4419739A Decentralized generation of synchronized clock control signals having dynamically selectable periods 失效
标题翻译：具有动态可选周期的同步时钟控制信号的分散式生成
公开(公告)号：US4419739A
公开(公告)日：1983-12-06
申请号：US342541
申请日：1982-01-25
申请人： Arnold Blum
发明人： Arnold Blum
IPC分类号： G06F1/04 , G06F1/10 , G06F9/00
CPC分类号： G06F1/10
摘要： In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connected to all of the T-rings by lines of equal length forces the individual T-rings to operate synchronously and keeps them operating in such a manner. In addition, reset circuitry is provided for forcing all of the T-rings to their first timing interval for initial synchronization thereof or, at an appropriate time, when a micro instruction requiring less than the maximum number of available T-ring timing signals is executed.The timing signals which are locally produced are subject to little delay on their way to the various local switching points. Thus, the entire system can be operated at a higher oscillator or master clock frequency to take advantage of the enhanced processing and transfer speeds of modern, highly integrated circuit chips.
摘要翻译：在由需要同步操作的几个电路化芯片组成的微程序处理器中，每个芯片都设有自己的本地时钟发生器或T形环，用于从微指令执行的子阶段所需的定时信号导出。通过相等长度的线路连接到所有T形环的主时钟迫使各个T形环同步工作并使它们以这种方式工作。此外，提供复位电路，用于迫使所有T形环的第一定时间隔用于其初始同步，或者在适当的时候，当执行需要小于最大数量的可用T形环定时信号的微指令时。本地产生的定时信号在到各种局部切换点的路上几乎没有延迟。因此，整个系统可以以更高的振荡器或主时钟频率工作，以利用现代高度集成的电路芯片的增强的处理和传输速度。

8. 发明授权

US5319948A Low temperature generation process and expansion engine 失效
标题翻译：低温发电过程和膨胀发动机
公开(公告)号：US5319948A
公开(公告)日：1994-06-14
申请号：US876273
申请日：1992-04-30
申请人： Arnold Blum , Manfred Schmidt
发明人： Arnold Blum , Manfred Schmidt
IPC分类号： F25B9/00 , F03G7/00 , F25B9/06 , F25B9/14
CPC分类号： F03G7/002 , F25B9/065 , F25B9/145 , F02G2243/52 , F25B2309/1402 , F25B2309/1408 , F25B2309/1425
摘要： In a low temperature generation process, compressed gas (3) at high pressure enters from an inlet nozzle (1) and alternately expands into one of two resonator tubes (A,B) of an expansion engine. The expanding gas excites standing acoustic waves (4) in the resonator tubes (A,B). The acoustic energy of the waves (4) is converted into electrical energy by acoustic/electric power converters and is led away outside the "cold area" of the tubes. The expansion engine contains one or more resonator tubes with a common inlet nozzle (1). Each resonator tube has an acoustic/electric power converter (5) and an exhaust port (6). Together with a compressor, a heat exchanger and a heat sink, the expansion engine provides a very effective cooling system which may be used for the cooling of small electronic devices like chips or modules.
摘要翻译：在低温发生过程中，高压下的压缩气体（3）从入口喷嘴（1）进入并交替地膨胀成膨胀发动机的两个谐振管（A，B）之一。膨胀气体激励谐振器管（A，B）中的驻波（4）。波浪（4）的声能通过声/电功率转换器转换成电能，并被引导到管的“冷区”之外。膨胀发动机包含一个或多个具有公共入口喷嘴（1）的谐振管。每个谐振器管具有声/电功率转换器（5）和排气口（6）。与压缩机，热交换器和散热器一起，膨胀发动机提供了非常有效的冷却系统，其可用于冷却诸如芯片或模块的小型电子设备。

9. 发明授权

US4688222A Built-in parallel testing circuit for use in a processor 失效
标题翻译：内置并行测试电路，用于处理器
公开(公告)号：US4688222A
公开(公告)日：1987-08-18
申请号：US810105
申请日：1985-12-17
申请人： Arnold Blum
发明人： Arnold Blum
IPC分类号： G06F11/22 , G06F11/27 , G01R31/28
CPC分类号： G06F11/27
摘要： The invention concerns arrangements and methods for error testing and diagnosing processors (e.g., 9; FIG. 2), whose logic subsystems (20) are interconnected by storage elements (23, 24) which in the error test and diagnostic mode are connected in the form of shift register means for the shift clock controlled application of test data and for receiving result data, and which comprise means (58) for comparing the actual result data with desired result data, said means setting an error indicator (59) for initiating further actions in the case of a mismatch. For testing the correct implementation of operations and operational secondary functions, a signature generator circuit (30) is provided comprising a test accumulator (51, 52, . . . , 5m) for accumulating the test and result data from the storage elements (23, 24) and a test clock generator and counter (28) for controlling the accumulation, as well as a test memory (29) providing test programs consisting of test data, desired result data and instructions to be tested of the processor instruction set. The signature generator circuit ( 30) is connected to an interface register (11, 12, . . . , 1m) and/or a system bus (8) of the processor, the stages of the interface register being included in the shift register means consisting of the storage elements (23, 24) at positions 21, 22, . . . , nm.
摘要翻译：本发明涉及用于对其逻辑子系统（20）由存储元件（23,24）进行互连的处理器（例如，9;图2）进行错误测试和诊断的布置和方法，所述存储元件在故障测试和诊断模式中被连接在用于移位时钟控制应用测试数据和接收结果数据的移位寄存器装置的形式，其包括用于将实际结果数据与期望结果数据进行比较的装置（58），所述装置设置用于进一步发起的错误指示符（59）在不匹配的情况下的行为。为了测试操作和操作次要功能的正确实现，提供了一种签名生成器电路（30），其包括用于累积来自存储元件（23,23）的测试和结果数据的测试累加器（51,52 ...，5m） 24）和用于控制累积的测试时钟发生器和计数器（28）以及提供由测试数据，期望结果数据和待处理指令集的指令组成的测试程序的测试存储器（29）。签名生成器电路（30）连接到处理器的接口寄存器（11,12，...，1m）和/或系统总线（8），接口寄存器的级包括在移位寄存器装置由位置21,22上的存储元件（23,24）组成。。。，nm。

10. 发明授权

US4030076A Processor nucleus combined with nucleus time controlled external registers integrated with logic and arithmetic circuits shared between nucleus and I/O devices 失效
标题翻译：处理器核与核时间控制的外部寄存器结合，与核和I / O设备之间共享的逻辑和运算电路集成
公开(公告)号：US4030076A
公开(公告)日：1977-06-14
申请号：US596487
申请日：1975-07-16
申请人： Arnold Blum , Johann Hajdu , Claus Erich Mohr , Leopold Reichl , Guenther Sonntag
发明人： Arnold Blum , Johann Hajdu , Claus Erich Mohr , Leopold Reichl , Guenther Sonntag
IPC分类号： G06F9/22 , G06F13/12 , G06F13/14 , G06F15/16 , G06F15/78 , G06F3/00 , G06F7/38 , G06F9/12
CPC分类号： G06F13/122 , G06F13/124 , G06F15/7832 , G06F15/7864 , G06F9/226
摘要： Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.
摘要翻译：与逻辑和运算电路集成的输入/输出寄存器在仅具有存储寄存器，指令解码逻辑，定时电路和算术和逻辑单元的处理器核的外部组合，用于执行微指令，从而使用输入/输出寄存器由微程序代码并且通过时间控制来选择性地执行用于输入和输出设备的所有适配器和接口通信和控制功能，或者选择性地切换到处理器核的数据流。

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