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1. 发明授权

US4109311A Instruction execution modification mechanism for time slice controlled data processors 失效
标题翻译：时间控制数据处理器的指令执行修改机制
公开(公告)号：US4109311A
公开(公告)日：1978-08-22
申请号：US725757
申请日：1976-09-23
申请人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Stephan Richter , Helmut Schaal , Hermann Schulze-Schoelling
发明人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Stephan Richter , Helmut Schaal , Hermann Schulze-Schoelling
IPC分类号： G06F12/00 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/318 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/06 , G06F15/16 , G06F15/177 , G06F9/19
CPC分类号： G06F9/4825 , G06F9/226 , G06F9/268 , G06F9/28 , G06F9/3851
摘要： An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions. If, during a given time slice interval, the program to be executed is on the modifiable program list and the instruction to be executed is on the modifiable instruction list and the appropriate condition is occurring in the data processing system, then the modification storage mechanism is enabled to send the modification signals for this instruction to the instruction execution unit for modifying the normal execution of this instruction.

2. 发明授权

US4095270A Method of implementing manual operations 失效
标题翻译：执行手册操作的方法
公开(公告)号：US4095270A
公开(公告)日：1978-06-13
申请号：US776576
申请日：1977-03-11
申请人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Guenter Knauft , Stephan Richter , Hermann Schulze-Schoelling
发明人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Guenter Knauft , Stephan Richter , Hermann Schulze-Schoelling
IPC分类号： G06F11/22 , G06F3/023 , G06F9/00 , G06F9/46 , G06F11/36 , G06F9/18
CPC分类号： G06F3/0232
摘要： A method for performing manual operations, such as address compare equal stop, single cycle alter, etc., in a time slice controlled microprocessor with microprogramming, which avoids stopping the processor clock when any of the programs requires a manual operation. This problem is solved by assigning the manual operations to a specific program, which for the other programs in the multiprogram environment executes the manual operations required.

3. 发明授权

US4295220A Clock check circuits using delayed signals 失效
标题翻译：使用延迟信号的时钟检查电路
公开(公告)号：US4295220A
公开(公告)日：1981-10-13
申请号：US98587
申请日：1979-11-29
申请人： Arnold Blum , Hellmuth R. Geng , Hermann Schulze-Schoelling , Bernd Spaeth
发明人： Arnold Blum , Hellmuth R. Geng , Hermann Schulze-Schoelling , Bernd Spaeth
IPC分类号： G01R31/28 , G01R31/3183 , G04D7/00 , H03K5/26 , H04M3/24 , H03K5/19 , G06F1/04
CPC分类号： H04M3/24 , H03K5/26
摘要： In a data processing or transmission system which includes at least two synchronized clocks, for example--T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock.Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
摘要翻译：在包括至少两个同步时钟的数据处理或传输系统中，例如T形环A和B，其产生用于微指令执行的定时脉冲Tai和Tbi，由从时钟接收脉冲的逻辑电路来检查同步。至少一个脉冲被延迟一个或多个脉冲周期持续时间ti。逻辑电路输出信号用作由独立的检查振荡器或时钟周期性地设置的指示器锁存器的输入。在优选实施例中，延迟由主 - 从触发器引入，主 - 从触发器接收T信号的预定组合并由独立检查时钟设置。延迟锁存器和关联的与门可以用于延迟和未延迟T信号的不同逻辑组合。该方案可以轻松扩展，以容纳两个以上的同步操作时钟。这些电路不仅检查时钟的瞬时同步，还检查时钟脉冲的正确排序。如果每个微指令执行的T形环计数器以可变数量的时钟脉冲操作，则该检查也是可行的。

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