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1. 发明授权

US4231085A Arrangement for micro instruction control 失效
标题翻译：微指令控制安排
公开(公告)号：US4231085A
公开(公告)日：1980-10-28
申请号：US934781
申请日：1978-08-18
申请人： Dieter Bazlen , Rolf Berger , Arnold Blum , Dietrich W. Bock , Herbert Chilinski , Hellmuth R. Geng , Johann Hajdu , Fritz Irro , Siegfried Neuber , Udo Wille
发明人： Dieter Bazlen , Rolf Berger , Arnold Blum , Dietrich W. Bock , Herbert Chilinski , Hellmuth R. Geng , Johann Hajdu , Fritz Irro , Siegfried Neuber , Udo Wille
IPC分类号： G06F9/22 , G06F9/12
CPC分类号： G06F9/226
摘要： In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.
摘要翻译：在微控制数据处理系统中，通过使用两个总线路径来将控制信号从微程序控制传送到由这些信号控制的集成电路模块所需的线和引脚的数量被保存，用于将控制信号分配到模块。专用于预解码控制信号功能的第一路径，并且共享用于传送数据和控制信号功能的第二路径。每个受控模块包括用于组合地解码通过两条路径接收的控制信号功能的附加解码电路。

2. 发明授权

US4398247A Control device for directing execution of forced operations in a data processing system 失效
标题翻译：用于在数据处理系统中指示强制操作的控制装置
公开(公告)号：US4398247A
公开(公告)日：1983-08-09
申请号：US186876
申请日：1980-09-12
申请人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
发明人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
IPC分类号： G06F9/48 , G06F9/26 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/46 , G06F9/18
CPC分类号： G06F9/3867 , G06F9/268 , G06F9/30145 , G06F9/3836
摘要： In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead.An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated.If the control signals need be grouped for physical reasons, it is possible to determine which of these signals are a function of forced operations. This will negate the need to otherwise distribute these control signals throughout the decoder, thereby reducing and simplifying the wiring required.
摘要翻译：在执行和控制特定程序的内部数据流时，通常需要通过插入适当数量的等待周期来延迟指令的执行。因此，可能需要中断指令执行，例如，将用于频道访问的给定数量的等待周期插入到数据处理系统的公共存储器中，用于重新加载数据或指令缓冲器或类似情况。在这种情况下，控制单元必须忽略等待执行的特定指令，而不是执行另一个强制操作。为NO OPERATION指令提供了一个适当的代码，比如说所有位为零。当执行强制操作时，可以在指令寄存器的输出端以较少的逻辑方式生成该代码。结果，在解码器的输出处没有控制信号有效。仅当要生成控制信号时，必须由解码器考虑指示强制操作的信号。如果控制信号由于物理原因需要分组，则可以确定这些信号中的哪一个是强制操作的功能。这将消除在整个解码器中分发这些控制信号的需要，从而减少和简化所需的布线。

3. 发明授权

US4400776A Data processor control subsystem 失效
标题翻译：数据处理器控制子系统
公开(公告)号：US4400776A
公开(公告)日：1983-08-23
申请号：US186883
申请日：1980-09-12
申请人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
发明人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
IPC分类号： G06F1/04 , G06F9/22 , G06F9/26 , G06F9/30 , G06F9/302 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3001 , G06F9/223 , G06F9/26 , G06F9/3869
摘要： An improved data processor control subsystem in which a cycle counter having a plurality of cascade-connected stages also comprises one or more supplemental or dummy stages, which can be selectively inserted or removed from the chain of cascade-connected stages, to alter the number of sub-cycles in an operating cycle, thereby decreasing the complexity of associated decoding circuitry.
摘要翻译：一种改进的数据处理器控制子系统，其中具有多个级联连接级的循环计数器还包括一个或多个补充或虚拟级，其可以从级联连接级链中选择性地插入或移除，以改变子周期，从而降低相关解码电路的复杂度。

4. 发明授权

US4656578A Device in the instruction unit of a pipeline processor for instruction interruption and repetition 失效
标题翻译：流水线处理器的指令单元中的器件用于指令中断和重复
公开(公告)号：US4656578A
公开(公告)日：1987-04-07
申请号：US646873
申请日：1984-09-04
申请人： Herbert Chilinski , Klaus J. Getzlaff , Johann Hajdu , Stephan Richter
发明人： Herbert Chilinski , Klaus J. Getzlaff , Johann Hajdu , Stephan Richter
IPC分类号： G06F9/38 , G06F11/14 , G06F13/00
CPC分类号： G06F9/3861 , G06F11/141
摘要： In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.
摘要翻译：在处理数据处理系统中的指令时，并不总是可以不间断地执行这些指令，因为特定情况下可能会发生以下所谓的事件，这就需要在继续中断指令处理之前执行由这些事件引起的操作的短暂中断。然而，仅当在中断期间包含指令的操作寄存器的内容被冻结时，这种重复才是可能的。这种情况需要两个动作：第一个是执行强制操作来解决事件。第二个动作是中断指令的指令和执行阶段的重复。

5. 发明授权

US4481575A Arrangement in a data processing system to reduce the cycle time 失效
标题翻译：在数据处理系统中进行排列以减少周期时间
公开(公告)号：US4481575A
公开(公告)日：1984-11-06
申请号：US352663
申请日：1982-02-26
申请人： Dieter Bazlen , Johann Hajdu , Gunter Knauft
发明人： Dieter Bazlen , Johann Hajdu , Gunter Knauft
IPC分类号： G06F7/00 , G06F1/06 , G06F1/10 , G06F1/12 , G06F7/48 , G06F9/38 , G06F1/04
CPC分类号： G06F7/48 , G06F9/3869
摘要： The cycle time of a data processing system should always be determined in such a manner that data from a source register, after having been propagated through, if necessary, several transfer sections and line drivers, and through a chain of logic circuits for the respective processing steps, can be stored in the result or sink register safely and even with the worst case propagation tolerance of all elements involved. The ideal cycle time therefore, which is dependent on the processing speed of the slowest chain of logic circuits, has to have added time segments for the worst case of unprecise clocking.A reduction of the cycle time by the above mentioned added time segments, and if necessary by the propagation delays in the transfer sections and in the line drivers, is achieved when the chain of logic circuits and thus its delay time is divided into two partial chains with the partial delays and if the sink register is arranged between the two partial chains. By thus splitting the chain of logic circuits into two partial chains, the logic partial functions can be executed during that time segment which is composed of the above mentioned added time segments.
摘要翻译：数据处理系统的周期时间应该总是以这样的方式来确定，即来自源寄存器的数据在必要时被传播通过若干传输部分和线路驱动器，并且通过用于相应处理的逻辑电路链步骤，可以安全地存储在结果或接收器寄存器中，甚至在涉及的所有元素的最差情况下传播容差。因此，理想的循环时间取决于最慢链逻辑电路的处理速度，必须为最不稳定的时钟的最坏情况添加时间段。当逻辑电路链和其延迟时间被分成两部分链时，通过上述添加的时间段减少循环时间，并且如果必要，通过传输部分和线路驱动器中的传播延迟来实现具有部分延迟，并且如果宿寄存器布置在两个部分链之间。通过这样将逻辑电路链分成两部分链，逻辑部分功能可以在由上述添加的时间段组成的时间段期间执行。

6. 发明授权

US4631663A Macroinstruction execution in a microprogram-controlled processor 失效
标题翻译：微程序控制处理器中的宏指令执行
公开(公告)号：US4631663A
公开(公告)日：1986-12-23
申请号：US500583
申请日：1983-06-02
申请人： Herbert Chilinski , Klaus J. Getzlaff , Johann Hajdu , Franz J. Raeth
发明人： Herbert Chilinski , Klaus J. Getzlaff , Johann Hajdu , Franz J. Raeth
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30 , G06F9/318 , G06F9/40
CPC分类号： G06F9/3017 , G06F9/223 , G06F9/26 , G06F9/30145 , G06F9/30189
摘要： In a microprogram-controlled processor, having an additional operating mode in which particular functions can be executed under direct hardware control, a mode latch signals whether microprogram instructions or directly controlled macro instructions are to be executed. The macroprogram instructions are conventionally executed. For the execution of directly controlled macro instructions, a control storage supplies a hardware control word associated with the macro instruction to be directly executed. The hardware control word contains a mode control bit for signalling that the direct hardware control mode is to be executed. The remainder of the hardware control word contains a plurality of direct control bits, each of which directly controls a hardware function. In an alternative embodiment multiple hardware control words are employed.
摘要翻译：在微程序控制的处理器中，具有其中可以在直接硬件控制下执行特定功能的附加操作模式，模式锁存器指示是否执行微程序指令或直接控制的宏指令。宏程序指令通常执行。为了执行直接控制的宏指令，控制存储器提供与要直接执行的宏指令相关联的硬件控制字。硬件控制字包含一个模式控制位，用于指示要执行直接硬件控制模式。硬件控制字的其余部分包含多个直接控制位，每个直接控制位直接控制硬件功能。在替代实施例中，采用多个硬件控制字。

7. 发明授权

US4030076A Processor nucleus combined with nucleus time controlled external registers integrated with logic and arithmetic circuits shared between nucleus and I/O devices 失效
标题翻译：处理器核与核时间控制的外部寄存器结合，与核和I / O设备之间共享的逻辑和运算电路集成
公开(公告)号：US4030076A
公开(公告)日：1977-06-14
申请号：US596487
申请日：1975-07-16
申请人： Arnold Blum , Johann Hajdu , Claus Erich Mohr , Leopold Reichl , Guenther Sonntag
发明人： Arnold Blum , Johann Hajdu , Claus Erich Mohr , Leopold Reichl , Guenther Sonntag
IPC分类号： G06F9/22 , G06F13/12 , G06F13/14 , G06F15/16 , G06F15/78 , G06F3/00 , G06F7/38 , G06F9/12
CPC分类号： G06F13/122 , G06F13/124 , G06F15/7832 , G06F15/7864 , G06F9/226
摘要： Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.
摘要翻译：与逻辑和运算电路集成的输入/输出寄存器在仅具有存储寄存器，指令解码逻辑，定时电路和算术和逻辑单元的处理器核的外部组合，用于执行微指令，从而使用输入/输出寄存器由微程序代码并且通过时间控制来选择性地执行用于输入和输出设备的所有适配器和接口通信和控制功能，或者选择性地切换到处理器核的数据流。

8. 发明授权

US5138707A Method of operating a timer in a digital data processing system 失效
标题翻译：在数字数据处理系统中操作定时器的方法
公开(公告)号：US5138707A
公开(公告)日：1992-08-11
申请号：US406628
申请日：1989-09-13
申请人： Wilhelm Haller , Johann Hajdu , Klaus J. Getzlaff
发明人： Wilhelm Haller , Johann Hajdu , Klaus J. Getzlaff
IPC分类号： G06F1/14 , H03K23/66
CPC分类号： H03K23/662 , G06F1/14
摘要： A method of operating a timer mechanism in a digital data processing system is described in which the contents of at least one timer register is updated by a predetermined time increment during each of successive periodic update cycles. Each update cycle includes a predetermined number of operating cycles of the data processing system. During each update cycle, the contents of an adjustment register is circularly shifted by one bit position and if the bit value at a particular position in this adjustment register has a predetermined binary value during an update cycle, then actual updating of the timer register is omitted during a related update cycle.

9. 发明授权

US5303365A Clock generation in a multi-chip computer system 失效
标题翻译：多芯片计算机系统中的时钟生成
公开(公告)号：US5303365A
公开(公告)日：1994-04-12
申请号：US715530
申请日：1991-06-14
申请人： Klaus J. Getzlaff , Johann Hajdu , Guenter Knauft
发明人： Klaus J. Getzlaff , Johann Hajdu , Guenter Knauft
IPC分类号： G06F1/04 , G06F1/10 , G06F1/12 , H03K5/15
CPC分类号： H03K5/15 , G06F1/10 , G06F1/12
摘要： The invention relates to a multi-chip computersystem with master-slave latches. It is known to provide all latches on all chips with two clock pulses, respectively. With the help of the latches the digital signals are pipelined through the logic gates on the chip. Due to tolerances, the edges which control the masters and the slaves have a skew. According to the invention, one of the two clock pulses is generated on the chip itself, respectively, by ANDing an auxiliary clock pulse with the other of the two clock pulses. This has the result, that the above mentioned edges of the two clock pulses occur almost at the same time with the consequence that the frequency of the clock pulses can be increased.
摘要翻译：本发明涉及具有主从锁存器的多芯片计算机系统。已知在所有芯片上分别提供两个时钟脉冲的所有锁存器。借助于锁存器，数字信号通过芯片上的逻辑门流水线化。由于公差，控制主机和从机的边缘有偏差。根据本发明，通过将辅助时钟脉冲与两个时钟脉冲中的另一个进行与运算，分别在芯片本身上产生两个时钟脉冲之一。这样做的结果是，两个时钟脉冲的上述边缘几乎同时出现，从而可以增加时钟脉冲的频率。

10. 发明授权

US4298980A LSI Circuitry conforming to level sensitive scan design (LSSD) rules and method of testing same 失效
标题翻译：符合级别敏感扫描设计（LSSD）规则的LSI电路和测试方法
公开(公告)号：US4298980A
公开(公告)日：1981-11-03
申请号：US60932
申请日：1979-07-26
申请人： Johann Hajdu , Guenter Knauft
发明人： Johann Hajdu , Guenter Knauft
IPC分类号： G01R31/28 , G01R31/3185 , G01T7/00 , H01L21/66 , H01L21/822 , H01L27/04 , G06F11/00
CPC分类号： G01R31/31853 , G01R31/318544
摘要： An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.
摘要翻译：一种LSI集成半导体电路系统，包括多个互连的最小可更换单元。系统和每个最小可更换单元完全符合“灵敏扫描设计（LSSD）规则”。 [水平敏感扫描设计规则在以下美国专利中的每一个中被完全公开和定义。第3,783,254,3,761,695,3,784,907号和EB Eichelberger和TW Williams出版的“A Logic Design Structure for LSI Testability”第14届设计自动化会议论文集，IEEE计算机学会，1977年6月20日至22日，第462-467页，新奥尔良，La。] 每个最小可替换单元包括具有多于两个移位寄存器级的移位寄存器段。每个最小可替换单元的每个移位寄存器段的每个寄存器级包括主触发器（锁存器）和从触发器（锁存器）。连接装置用于将所述最小可更换单元的移位寄存器段连接成单个移位寄存器。提供了包括测试组合电路装置的附加可控电路装置，用于仅在所述最小可更换单元的每个移位寄存器段的所述前两级设置预定模式。附加电路装置有助于和用于测试每个最小可更换单元的电路完整性（卡住故障和连续性）。

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