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1. 发明申请

US20180239738A1 SCALABLE 2.5D INTERFACE CIRCUITRY 审中-公开
公开(公告)号：US20180239738A1
公开(公告)日：2018-08-23
申请号：US15954078
申请日：2018-04-16
申请人： Altera Corporation
发明人： Chee Hak Teh , Arifur Rahman
IPC分类号： G06F15/78 , G06F1/08 , G06F13/40 , G06F13/42
CPC分类号： G06F15/7803 , G06F1/06 , G06F1/10 , G06F13/4022 , G06F13/4234 , G06F13/4291 , G06F15/7864 , Y02D10/14 , Y02D10/151
摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

2. 发明申请

US20150370754A1 INTEGRATED CIRCUIT APPARATUS, THREE-DIMENSIONAL INTEGRATED CIRCUIT, THREE-DIMENSIONAL PROCESSOR DEVICE, AND PROCESS SCHEDULER, WITH CONFIGURATION TAKING ACCOUNT OF HEAT 审中-公开
标题翻译：集成电路设备，三维集成电路，三维处理器器件和处理器调度器，配置加热器
公开(公告)号：US20150370754A1
公开(公告)日：2015-12-24
申请号：US14800979
申请日：2015-07-16
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： Takashi MORIMOTO , Kouji KAI
IPC分类号： G06F15/78 , G06F1/20
CPC分类号： G06F15/7864 , G05F5/00 , G06F1/20 , G06F12/0893 , G06F15/80 , G06F2212/601 , H01L23/34 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/1116 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06565 , H01L2225/06589 , H01L2924/1432 , H01L2924/1434 , H01L2924/15311
摘要： The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit. The first circuit is partitioned into a plurality of circuit blocks according to the distance from the arranged position of the second circuit, and the control circuit controls the partitioned respective circuit blocks separately.
摘要翻译：本发明提供了一种三维集成电路，其中可以抑制由于集中产生的热而产生作为高温部分的热点的三维集成电路。集成电路装置包括：第一电路，由存储电路，第二由运算电路构成的电路，以及控制电路。根据与第二电路的布置位置的距离，第一电路被划分为多个电路块，并且控制电路分别控制分隔的各个电路块。

3. 发明授权

US09075929B2 Issuing requests to a fabric 有权
公开(公告)号：US09075929B2
公开(公告)日：2015-07-07
申请号：US14578720
申请日：2014-12-22
申请人： Intel Corporation
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F3/00 , G06F5/00 , G06F13/42 , G06F13/368
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

4. 发明授权

US07512731B2 Computer system and memory bridge for processor socket thereof 有权
标题翻译：用于处理器插座的计算机系统和存储器桥
公开(公告)号：US07512731B2
公开(公告)日：2009-03-31
申请号：US11378387
申请日：2006-03-20
申请人： Shan-Kai Yang , Wen-Der Kao
发明人： Shan-Kai Yang , Wen-Der Kao
IPC分类号： G06F13/00 , G06F13/36 , G06F13/40 , G06F13/42
CPC分类号： G06F13/4027 , G06F15/7864
摘要： A multi-processor computer system includes a memory bridge configured in a processor socket on a motherboard. The memory bridge module electrically connects a processor bus and a memory bus that connect to the processor socket. Thus, an adjacent processor is capable of accessing an unused memory by way of the processor bus, the memory bridge and the memory bus.
摘要翻译：多处理器计算机系统包括配置在主板上的处理器插槽中的存储器桥。存储器桥模块电连接处理器总线和连接到处理器插槽的存储器总线。因此，相邻处理器能够通过处理器总线，存储器桥和存储器总线访问未使用的存储器。

5. 发明申请

US20090055157A1 Server Having Remotely Manageable Emulated Functions 审中-公开
标题翻译：服务器具有可远程管理的仿真功能
公开(公告)号：US20090055157A1
公开(公告)日：2009-02-26
申请号：US12197532
申请日：2008-08-25
申请人： Aviv Soffer
发明人： Aviv Soffer
IPC分类号： G06F9/455
CPC分类号： G06F15/7864 , Y02D10/13
摘要： A new and unique server having server core, storage interface I/O function, local area network interface I/O function that comprises remote graphic controller manageable emulated function (RMEF). The RMEF comprises circuitry capable of emulating a standard graphic controller to the server core so as to enable the core to generate video frames and circuitry capable of remotely delivering the video frames to remote management console application and other I/O interface functions. The functions can be implemented on a single chip.
摘要翻译：具有服务器核心，存储接口I / O功能，包括远程图形控制器可管理仿真功能（RMEF）的局域网接口I / O功能）的新型独特服务器。 RMEF包括能够将标准图形控制器模拟到服务器核心的电路，以便使核心能够产生能够将视频帧远程传送到远程管理控制台应用程序和其他I / O接口功能的视频帧和电路。这些功能可以在单个芯片上实现。

6. 发明申请

US20080030510A1 Multi-GPU rendering system 审中-公开
标题翻译：多GPU渲染系统
公开(公告)号：US20080030510A1
公开(公告)日：2008-02-07
申请号：US11497417
申请日：2006-08-02
申请人： Min-Chuan Wan , His-Jou Deng , Chuncheng Lin
发明人： Min-Chuan Wan , His-Jou Deng , Chuncheng Lin
IPC分类号： G06F15/80
CPC分类号： G06F15/7864 , G06T1/20
摘要： A multi-GPU rendering system according to a preferred embodiment of the present invention includes a CPU, a chipset, the first GPU (graphics processing unit), the first graphics memory for the first GPU, a second GPU, and the second graphics memory for the second GPU. The chipset is electrically connected to the CPU, the first GPU and the second GPU. Graphics content is divided into two parts for the two GPUs to process separately. The two parts of the graphics content may be the same or different in sizes. Two processed graphics results are combined in one of these two graphics memories to form complete image stream and then it is outputted to a display by the GPU.
摘要翻译：根据本发明的优选实施例的多GPU渲染系统包括CPU，芯片组，第一GPU（图形处理单元），用于第一GPU的第一图形存储器，第二GPU以及第二图形存储器第二个GPU。芯片组电连接到CPU，第一GPU和第二GPU。图形内容分为两部分，用于两个GPU单独处理。图形内容的两个部分的尺寸可以相同或不同。两个处理的图形结果组合在这两个图形存储器之一中以形成完整的图像流，然后由GPU输出到显示器。

7. 发明申请

US20070113048A1 Low-Power Co-Processor Architecture 有权
标题翻译：低功耗协处理器架构
公开(公告)号：US20070113048A1
公开(公告)日：2007-05-17
申请号：US11557755
申请日：2006-11-08
申请人： Marc Royer , Bharath Siravara , Steven Bartling , Charles Branch , Pedro Galabert , Neeraj Mogotra , Sunil Kamath
发明人： Marc Royer , Bharath Siravara , Steven Bartling , Charles Branch , Pedro Galabert , Neeraj Mogotra , Sunil Kamath
IPC分类号： G06F15/00 , G06F12/00
CPC分类号： G06F15/7864 , G06F9/3879 , Y02D10/13
摘要： A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.
摘要翻译：公开了一种包括协处理器和存储器交换机资源的系统架构。存储器开关包括多个存储器块和用于可选择地将协处理器的处理单元耦合的开关电路，以及耦合到系统的系统总线的总线从属电路到选择的存储器块。存储器开关可以被构造为多路复用器的阵列，其由存储器开关的控制逻辑控制，以响应于控制寄存器的内容。协处理器的各种处理单元各自能够直接访问由开关电路控制的存储块之一。在由处理单元之一处理数据块之后，存储器开关将存储器块与其他功能单元相关联，从而将数据从一个功能单元移动到另一个功能单元，而不需要读取和重写数据。

8. 发明申请

US20060149883A1 Systems and methods for providing co-processors to computing systems 有权
标题翻译：为计算系统提供协处理器的系统和方法
公开(公告)号：US20060149883A1
公开(公告)日：2006-07-06
申请号：US11324918
申请日：2006-01-04
申请人： James Benbow , Gary Finley , Ravi Chandran , Nathan Woods , Roman Kononov
发明人： James Benbow , Gary Finley , Ravi Chandran , Nathan Woods , Roman Kononov
IPC分类号： G06F13/14
CPC分类号： H05K1/141 , G06F1/184 , G06F1/185 , G06F1/186 , G06F15/7864 , H05K2201/049 , H05K2201/10212 , H05K2201/10704 , H05K2201/10734
摘要： Computing systems with conventional CPUs coupled to co-processors or accelerators implemented in FPGAs (Field Programmable Gate Arrays). One embodiment of the systems and methods according to the invention includes a FPGA accelerator implemented in a computer system by providing an adapter board configured to be used in a standard CPU socket.
摘要翻译：具有耦合到FPGA（现场可编程门阵列）中实现的协处理器或加速器的常规CPU的计算系统。根据本发明的系统和方法的一个实施例包括通过提供配置成在标准CPU插槽中使用的适配器板在计算机系统中实现的FPGA加速器。

9. 发明申请

US20060106591A1 System with PPU/GPU architecture 有权
标题翻译：具有PPU / GPU架构的系统
公开(公告)号：US20060106591A1
公开(公告)日：2006-05-18
申请号：US10988588
申请日：2004-11-16
申请人： Jean Bordes , Curtis Davis , Manju Hegde
发明人： Jean Bordes , Curtis Davis , Manju Hegde
IPC分类号： G06F9/45
CPC分类号： G06F15/7864
摘要： A PPU-enhanced system is described in which a Physics Processing Unit (PPU) and a Graphics Processing Unit (GPU) are connected with the system.
摘要翻译：描述了一种PPU增强系统，其中物理处理单元（PPU）和图形处理单元（GPU）与系统连接。

10. 发明申请

US20050273542A1 Configurable communication template for designing and implementing an accelerator 失效
标题翻译：用于设计和实现加速器的可配置通信模板
公开(公告)号：US20050273542A1
公开(公告)日：2005-12-08
申请号：US10863550
申请日：2004-06-08
申请人： Ramanujan Valmiki , Ashok Halambi , Madhuri Mandava , Seru Srinivas , Shashank Dabral , Marimuthu Kumar , William Salefski
发明人： Ramanujan Valmiki , Ashok Halambi , Madhuri Mandava , Seru Srinivas , Shashank Dabral , Marimuthu Kumar , William Salefski
IPC分类号： G06F13/00 , G06F15/78 , G06F17/50
CPC分类号： G06F17/5045 , G06F15/7864
摘要： A system and method of designing an accelerator for a processor-based system. The accelerator design problem is partitioned into a data communicate module design problem and a data compute core module design problem. The hardware design of the data communicate module is achieved through a predetermined communication template which is customized for the particular application. The communication template has individual configurable communication components and a programmable control flow path. The components of the communicate template include a host bus interface, a memory bus interface, a direct memory access, a local memory and a control module. The combination of the communication components in a single configurable communication template and their optimized interconnections increase the speed of data transfer and data control processes in the accelerator. The hardware design of the data compute core module can be achieved through custom hardware design or by automatically generating hardware from software description.
摘要翻译：一种为基于处理器的系统设计加速器的系统和方法。加速器设计问题分为数据通信模块设计问题和数据计算核心模块设计问题。数据通信模块的硬件设计是通过针对特定应用定制的预定通信模板来实现的。通信模板具有单独的可配置通信组件和可编程控制流程路径。通信模板的组件包括主机总线接口，存储器总线接口，直接存储器访问，本地存储器和控制模块。单个可配置通信模板中的通信组件与其优化的互连的组合增加了加速器中数据传输和数据控制过程的速度。数据计算核心模块的硬件设计可以通过定制硬件设计或通过软件描述自动生成硬件来实现。

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