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1. 发明授权

US09971733B1 Scalable 2.5D interface circuitry 有权
公开(公告)号：US09971733B1
公开(公告)日：2018-05-15
申请号：US14960175
申请日：2015-12-04
申请人： Altera Corporation
发明人： Chee Hak Teh , Arifur Rahman
IPC分类号： G06F13/00 , G06F13/40 , G06F13/38 , G06F15/78 , G06F1/08 , G06F13/42
CPC分类号： G06F15/7803 , G06F1/08 , G06F13/4022 , G06F13/4234 , G06F13/4291 , G06F15/7864
摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

2. 发明申请

US20140281383A1 GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE 有权
标题翻译：接地参考单端信号连接图形处理单元多芯片模块
公开(公告)号：US20140281383A1
公开(公告)日：2014-09-18
申请号：US13973952
申请日：2013-08-22
申请人： NVIDIA Corporation
发明人： William J. Dally , Jonah M. Alben , John W. Poulton , Thomas Hastings Greer, III
IPC分类号： G06F15/78
CPC分类号： G06F15/7864 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2924/15192 , H01L2924/15311
摘要： A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-, ended signaling interface advantageously implements ground-referenced single-ended signaling.
摘要翻译：包括多芯片模块（MCM）的互连芯片的系统包括处理器芯片，系统功能芯片和被配置为包括处理器芯片，系统功能芯片和互连电路的MCM封装。处理器芯片被配置为包括第一接地参考的单端信令接口电路。在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。系统功能芯片被配置为包括第二单端信令接口电路和主机接口。 MCM封装中制造的第二组电迹线，用于将主机接口耦合到MCM封装的至少一个外部引脚。在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

3. 发明授权

US08805926B2 Common idle state, active state and credit management for an interface 有权
标题翻译：公共空闲状态，接口的活动状态和信用管理
公开(公告)号：US08805926B2
公开(公告)日：2014-08-12
申请号：US13248232
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Robert P. Adler , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Robert P. Adler , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
IPC分类号： G06F15/16
CPC分类号： G06F13/42 , G06F9/466 , G06F15/7825 , G06F15/7864 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于输入耦合到结构的代理的代理状态机的信用初始化状态以便初始化该结构的交易信用跟踪器中的信用的方法。该跟踪器跟踪给定交易类型的代理的第一渠道的交易队列的信用。然后，代理可以断言信用初始化信号，以使得信用被存储在与第一交易类型的代理的第一渠道的交易队列的数量相对应的交易信用跟踪器中。描述和要求保护其他实施例。

4. 发明申请

US20130086586A1 Issuing Requests To A Fabric 有权
公开(公告)号：US20130086586A1
公开(公告)日：2013-04-04
申请号：US13248276
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F9/46
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

5. 发明授权

US07475175B2 Multi-processor module 失效
标题翻译：多处理器模块
公开(公告)号：US07475175B2
公开(公告)日：2009-01-06
申请号：US10800837
申请日：2004-03-15
申请人： David A. Klein , Christian L. Belady , Shaun L. Harris , Michael C. Day , Jeffrey P. Christenson , Brent A. Boudreaux , Stuart C. Haden , Eric Peterson , Jeffrey N. Metcalf , James S. Wells , Gary W. Williams , Paul A. Wirtzberger , Roy M. Zeighami , Greg Huff
发明人： David A. Klein , Christian L. Belady , Shaun L. Harris , Michael C. Day , Jeffrey P. Christenson , Brent A. Boudreaux , Stuart C. Haden , Eric Peterson , Jeffrey N. Metcalf , James S. Wells , Gary W. Williams , Paul A. Wirtzberger , Roy M. Zeighami , Greg Huff
IPC分类号： H01L23/34 , H01L23/12 , H05K7/20 , G06F13/00
CPC分类号： G06F15/0216 , G06F15/7864
摘要： An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.
摘要翻译：一种装置包括多个逻辑上独立的处理器，系统总线以及与多个处理器通信的高速缓存控制和总线桥接器件，使得高速缓存控制和总线桥接器件被逻辑地插入在处理器和系统总线之间，以及其中所述处理器和高速缓存控制和总线桥接器件以模块形式被布置，使得所述设备是用于标准单处理器模块的插入式替换。

6. 发明申请

US20060161710A1 Single board computer for industry personal computer 审中-公开
标题翻译：行业个人电脑的单板电脑
公开(公告)号：US20060161710A1
公开(公告)日：2006-07-20
申请号：US11288109
申请日：2005-11-29
申请人： Chia Liu
发明人： Chia Liu
IPC分类号： H05K7/10 , G06F13/00
CPC分类号： G06F15/7864
摘要： A single board computer for an industry personal computer is disclosed. The single board computer comprises a CPU, a memory controller hub, and input/out zones, wherein at least one of the input/output zones is provided with a connector, the connector being dedicated for transporting a differential signal and connected with a wiring zone dedicated for differential signal on the single board computer, and being adapted to receive an interface card in compliance with a protocol for differential signal transport.
摘要翻译：公开了用于工业个人计算机的单板计算机。单板计算机包括CPU，存储器控制器集线器和输入/输出区域，其中输入/输出区域中的至少一个设置有连接器，该连接器专用于传送差分信号并与布线区域连接专用于单板计算机上的差分信号，并适用于接收符合差分信号传输协议的接口卡。

7. 发明授权

US07062769B1 Object-oriented processor design and design methodologies 有权
标题翻译：面向对象的处理器设计和设计方法
公开(公告)号：US07062769B1
公开(公告)日：2006-06-13
申请号：US09348783
申请日：1999-07-07
申请人： Wei Ma , K. Y. Martin Lee , Kambiz Homayounfar
发明人： Wei Ma , K. Y. Martin Lee , Kambiz Homayounfar
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F15/7864
摘要： A distributed processing system having a host processor including a host communication infrastructure (HCI) configured for communication with said host processor; a plurality of class processors each having an associated private localized read/write memory; and a plurality of application program interface modules each configured to provide an interface between said host communication infrastructure and at least one said class processor, wherein each said class processor responds to selected data messages on said HCI to perform selected computations utilizing said read/write memory. This embodiment provides an ideal architecture for fabrication on a single chip and avoids processor and bus bottlenecks by providing distributed processing power with local memory for each class processor.Also provided is a method for designing a distributed processing system for an application. The method includes steps of partitioning the application into functions and data messages; configuring a host processor having a host communication infrastructure (HCI) to pass data messages via the HCI to control the application; configuring a plurality of class processors to compute the functions into which the application is partitioned in response to the data messages; and interconnecting the class processors to the host processor via application program interface modules in a star configuration. Systems designed in accordance with this method embodiment are well-suited for integration on a single chip, and can be easily updated and modified as necessary, because changes made to a class processor have minimal effect on the remainder of the system.
摘要翻译：一种具有主处理器的分布式处理系统，所述主机处理器包括被配置为与所述主机处理器进行通信的主机通信基础设施（HCI）多个类处理器，每个具有关联的专用局部读/写存储器; 以及多个应用程序接口模块，每个应用程序接口模块被配置为提供所述主机通信基础设施和至少一个所述类别处理器之间的接口，其中每个所述类处理器响应所述HCI上的所选择的数据消息，以利用所述读/写存储器执行所选择的计算。该实施例提供了用于在单个芯片上制造的理想架构，并且通过为每个类处理器提供具有本地存储器的分布式处理能力来避免处理器和总线瓶颈。还提供了一种用于设计用于应用的分布式处理系统的方法。该方法包括将应用程序划分为功能和数据消息的步骤; 配置具有主机通信基础设施（HCI）的主处理器以经由HCI传递数据消息以控制应用; 配置多个类处理器以响应于所述数据消息来计算应用程序被分割成的功能; 并通过星型配置中的应用程序接口模块将类处理器与主机处理器互连。根据该方法实施例设计的系统非常适合于在单个芯片上集成，并且可以根据需要容易地更新和修改，因为对类处理器的改变对系统的其余部分具有最小的影响。

8. 发明申请

US20040225821A1 Multi-processor module 失效
标题翻译：多处理器模块
公开(公告)号：US20040225821A1
公开(公告)日：2004-11-11
申请号：US10800837
申请日：2004-03-15
发明人： David A. Klein , Christian L. Belady , Shaun L. Harris , Michael C. Day , Jeffrey P. Christenson , Brent A. Boudreaux , Stuart C. Haden , Eric Peterson , Jeffrey N. Metcalf , James S. Wells , Gary W. Williams , Paul A. Wirtzberger , Roy M. Zeighami , Greg Huff
IPC分类号： G06F013/36
CPC分类号： G06F15/0216 , G06F15/7864
摘要： An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.
摘要翻译：一种装置包括多个逻辑上独立的处理器，系统总线以及与多个处理器通信的高速缓存控制和总线桥接器件，使得高速缓存控制和总线桥接器件被逻辑地插入在处理器和系统总线之间，以及其中所述处理器和高速缓存控制和总线桥接器件以模块形式被布置，使得所述设备是用于标准单处理器模块的插入式替换。

9. 发明申请

US20040046761A1 System-on-a-chip controller 失效
标题翻译：系统级芯片控制器
公开(公告)号：US20040046761A1
公开(公告)日：2004-03-11
申请号：US10185791
申请日：2002-06-28
申请人： Oak Technology, Ink
发明人： Timothy M. Hellman , Neil B. Epstein , Steven J. Pratt , Fred W. Andree , Karl M. Marks , Joerg Landmann , James W. Brissette
IPC分类号： G06F015/16 , G06F013/14
CPC分类号： G06F9/30185 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/345 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F15/7864 , G06T1/20
摘要： A system-on-a-chip controller having a first processor and a second processor. The first processor provides control processing and image processing. The second processor provides image processing. The processors receive data from an external source through a data bus. Also, the controller can include a third controller to provide I/O functionality to an external device. The second processor processes the stored data in either a row or column configuration. A fixed-length instruction word can be decoded into two instructions, an operation instruction and an I/O instruction, and can be used to process the data. The I/O instruction can be disposed in an unused bit field of the operation instruction.
摘要翻译：一种具有第一处理器和第二处理器的片上系统控制器。第一个处理器提供控制处理和图像处理。第二处理器提供图像处理。处理器通过数据总线从外部源接收数据。此外，控制器可以包括第三控制器以向外部设备提供I / O功能。第二个处理器以行或列配置处理存储的数据。固定长度指令字可以被解码为两个指令，一个操作指令和一个I / O指令，并且可以用于处理数据。 I / O指令可以设置在操作指令的未使用位字段中。

10. 发明申请

US20030028751A1 Modular accelerator framework 审中-公开
标题翻译：模块化加速器框架
公开(公告)号：US20030028751A1
公开(公告)日：2003-02-06
申请号：US09922516
申请日：2001-08-03
发明人： Robert G. McDonald , Barry D. Williamson , Micah R. McDaniel
IPC分类号： G06F015/00
CPC分类号： G06F17/5045 , G06F15/7864
摘要： An acceleration engine may include a set of accelerators and a set of resources coupled to the accelerators. The resources may interface the accelerators to an interconnect, and may provide a programming interface to the accelerators. Since the resources handle interfacing the accelerators to a given interconnect, the accelerators may be insulated from the details of a given system. If more than one accelerator is included in the acceleration engine, some of the resources may be shared by the accelerators. For example, if the resources include a memory for storing data accessed by an accelerator, the memory may be shared between by the accelerators. A methodology for creating an acceleration engine is also described.
摘要翻译：加速引擎可以包括一组加速器和一组耦合到加速器的资源。资源可以将加速器连接到互连，并且可以向加速器提供编程接口。由于资源处理将加速器连接到给定的互连，加速器可以与给定系统的细节绝缘。如果加速引擎中包含多个加速器，则某些资源可能由加速器共享。例如，如果资源包括用于存储由加速器访问的数据的存储器，则存储器可以由加速器共享。还描述了用于创建加速引擎的方法。

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