专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4189773A On-line memory space allocation 失效
标题翻译：在线内存空间分配
公开(公告)号：US4189773A
公开(公告)日：1980-02-19
申请号：US485572
申请日：1974-07-03
申请人： Michael F. O'Meara
发明人： Michael F. O'Meara
IPC分类号： G05B19/05 , G06F9/19
CPC分类号： G05B19/056 , G05B2219/13153 , G05B2219/15065 , G05B2219/36078
摘要： A programmable data processor or controller serving as the main control in a control system contains an executive program for controlling the transfer of information between the processor and system equipment, updating that information during on-line control of the equipment and modifying the executive program to change operating parameters of the system while the data processor is controlling the system equipment. Modification of the executive program and displaying of system parameters relative to the executive program and the system equipment is accomplished through the use of an operator's console which communicates with the data processor and system equipment as a result of operator intervention.
摘要翻译：作为控制系统中的主要控制器的可编程数据处理器或控制器包括用于控制处理器和系统设备之间的信息传送的执行程序，在设备的在线控制期间更新该信息并修改执行程序以改变数据处理器控制系统设备时系统的运行参数。执行程序的修改和相对于执行程序和系统设备的系统参数的显示是通过使用由于操作员干预而与数据处理器和系统设备通信的操作员控制台而实现的。

2. 发明授权

US4109311A Instruction execution modification mechanism for time slice controlled data processors 失效
标题翻译：时间控制数据处理器的指令执行修改机制
公开(公告)号：US4109311A
公开(公告)日：1978-08-22
申请号：US725757
申请日：1976-09-23
申请人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Stephan Richter , Helmut Schaal , Hermann Schulze-Schoelling
发明人： Arnold Blum , Horst VON DER Heyden , Fritz Irro , Stephan Richter , Helmut Schaal , Hermann Schulze-Schoelling
IPC分类号： G06F12/00 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/318 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/06 , G06F15/16 , G06F15/177 , G06F9/19
CPC分类号： G06F9/4825 , G06F9/226 , G06F9/268 , G06F9/28 , G06F9/3851
摘要： An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions. If, during a given time slice interval, the program to be executed is on the modifiable program list and the instruction to be executed is on the modifiable instruction list and the appropriate condition is occurring in the data processing system, then the modification storage mechanism is enabled to send the modification signals for this instruction to the instruction execution unit for modifying the normal execution of this instruction.

3. 发明授权

US4034351A Method and apparatus for transmitting common information in the information processing system 失效
标题翻译：用于在信息处理系统中传送公共信息的方法和装置
公开(公告)号：US4034351A
公开(公告)日：1977-07-05
申请号：US657662
申请日：1976-02-12
申请人： Fumihiko Takezoe
发明人： Fumihiko Takezoe
IPC分类号： G06F13/00 , G06F15/16 , G06F15/173 , H04L12/42 , G06F3/04 , G06F7/10 , G06F9/19 , G08B11/00
CPC分类号： H04L12/42
摘要： In an information processing system of the type having widely dispersed terminals tied together by a series communications link, common data which is of interest to all stations is collected and registered in a simplified manner. The common information, consisting of the status of each of the stations, is collected by any station sending out a search instruction as part of an information word. As the information word passes through each successive station, each respective station adds a status bit to the information word indicating the status thereof. When the new-completed information word returns to the originating station, the common data is registered and displayed. Also the common data is sent, along with a "register common data" instruction, to all other stations via the communication link. Upon receipt of such information and instruction, each station registers and displays the common data.
摘要翻译：在具有通过串联通信链路连接在一起的广泛分散的终端的信息处理系统中，以简化的方式收集和登记所有站点感兴趣的公共数据。由每个站的状态组成的公共信息由发送搜索指令的任何站作为信息字的一部分收集。当信息字通过每个连续的站时，每个相应的站将一个状态位添加到指示其状态的信息字。当新完成的信息字返回到始发站时，登记并显示公共数据。此外，公共数据连同“寄存器公共数据”指令通过通信链路发送到所有其他站。接收到这样的信息和指令后，每个站点注册并显示公共数据。

4. 发明授权

US3718912A Instruction execution unit 失效
标题翻译：指示执行单位
公开(公告)号：US3718912A
公开(公告)日：1973-02-27
申请号：US3718912D
申请日：1970-12-22
申请人： IBM
发明人： HASBROUCK L , MADDEN B , WIERZBICKI J , REW R , SUSSENGUTH E
IPC分类号： G06F9/318 , G06F9/38 , G06F9/19
CPC分类号： G06F9/3836 , G06F9/30072 , G06F9/30192 , G06F9/3838 , G06F9/384 , G06F9/3889
摘要： An execution system for instructions having source and sink operand designations includes an arithmetic unit, execution means for holding an instruction for controlling the arithmetic unit and a plurality of operand registers, each having tag means associated therewith for indicating the nature of data stored therein. Instruction modification logic, on the basis of indications of availability of the operand registers, inserts modified source and sink operand register designations in instructions which are then stored in an instruction register stack. Interlock logic controls the transfer of instructions from the instruction register stack to the execution means as a function of the source and sink operand register designations in the modified instructions and the data tags associated with the operand registers.
摘要翻译：用于具有源和汇操作数指定的指令的执行系统包括运算单元，用于保存用于控制算术单元的指令和多个操作数寄存器的执行装置，每个具有与其相关联的标签装置，用于指示存储在其中的数据的性质。指令修改逻辑基于操作数寄存器可用性的指示，将指令中的修改后的源和汇操作数寄存器指定插入指令寄存器堆栈中。互锁逻辑控制从指令寄存器堆栈到执行装置的指令的传输，作为修改后的指令中的源和汇操作数寄存器指定和与操作数寄存器相关联的数据标签的函数。

5. 发明授权

US4447871A Data communication system with a front-end-processor 失效
标题翻译：具有前端处理器的数据通信系统
公开(公告)号：US4447871A
公开(公告)日：1984-05-08
申请号：US230805
申请日：1981-02-02
申请人： Matsuaki Terada , Koji Yokota
发明人： Matsuaki Terada , Koji Yokota
IPC分类号： G06F13/12 , G06F13/42 , G06F15/16 , G06F9/19
CPC分类号： G06F13/128 , G06F13/4213
摘要： A data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor, which preprocesses the received data, and transfers the pre-processed data to the computer through the bus. By operating the front-end-processors in parallel with respect to successively received packets of data, the processing speed of the system is increased.
摘要翻译：一种包括数据分配器，通信站和多个前端处理器的数据通信系统。这些前端处理器通过公共总线与计算机连接。分配器将站接收的数据分配给一个可用的前端处理器，该前端处理器对接收的数据进行预处理，并通过总线将预处理的数据传送到计算机。通过相对于连续接收的数据包并行操作前端处理器，系统的处理速度增加。

6. 发明授权

US4425618A Method and apparatus for introducing program changes in program-controlled systems 失效
标题翻译：在程序控制系统中引入程序变更的方法和装置
公开(公告)号：US4425618A
公开(公告)日：1984-01-10
申请号：US323812
申请日：1981-11-23
申请人： Thomas P. Bishop , Susan J. Picus
发明人： Thomas P. Bishop , Susan J. Picus
IPC分类号： G06F9/46 , G06F7/00 , G06F7/02 , G06F9/00 , G06F9/06 , G06F9/445 , G06F9/19
CPC分类号： G06F8/67 , G05B2219/23327 , G05B2219/23329
摘要： An arrangement for introducing modifications in the program of a program-controlled system. Each time a modified version of a selected program function is stored in the system, it is tagged with a function sequence number; meanwhile, the original version of the program function is retained in the system. Each time a program process is initiated, it is tagged with a process sequence number. The two types of sequence numbers are assigned from a common source. Whenever the selected program function is called by a program process, a comparison is made between the process sequence number and the function sequence number. If the comparison indicates that the process was initiated before the modification was stored in the system, the original version of the selected program function is executed; otherwise, the modified version is executed. Thus, the original version or the modified version is used consistently throughout the active life of a process.
摘要翻译：用于在程序控制系统的程序中引入修改的布置。每次将所选程序功能的修改版本存储在系统中时，将使用功能序列号进行标记; 同时，程序功能的原始版本保留在系统中。每次启动程序进程时，都会使用进程序列号进行标记。两种类型的序列号从公共源分配。无论何时通过程序进程调用所选择的程序功能，都可以对过程序列号和功能序列号进行比较。如果比较表明该过程在修改存储在系统中之前启动，则执行所选程序功能的原始版本; 否则，执行修改版本。因此，原始版本或修改版本在整个流程的整个活动期间始终被使用。

7. 发明授权

US3731282A Multifunction routing network 失效
标题翻译：多功能路由网络
公开(公告)号：US3731282A
公开(公告)日：1973-05-01
申请号：US3731282D
申请日：1971-08-27
申请人： ALLIED MANAGEMENT & SYSTEMS CO
发明人： DANCIS D , DORFUSS G , ZITRON B
IPC分类号： G06F3/153 , G06F13/38 , G09B7/08 , G06F9/19 , G06F3/00 , G06F15/56
CPC分类号： G09B7/08 , G06F3/153 , G06F13/38
摘要： A multifunction routing network. The routing network is provided with a function control means including a condition responsive logic network having an iterative multifunction control loop. Register and memory means are also provided in the routing network which are operatively associated with the control means for providing input conditions thereto and for receiving output conditions therefrom. The logic network is provided with a multistable means having a plurality of states and is responsive to the states thereof and the input conditions thereto to provide a plurality of control functions of both a data control and an execute non-data control nature for the routing network. A computer, an input keyboard, an audio-visual playback device, and a television are also provided which are operatively associated with the register and memory means for providing input conditions thereto and for responding to output conditions therefrom.
摘要翻译：多功能路由网络。路由网络设置有包括具有迭代多功能控制环路的条件响应逻辑网络的功能控制装置。在路由网络中还提供寄存器和存储器装置，其与控制装置可操作地相关联，用于向其提供输入条件并用于从其接收输出条件。逻辑网络具有多状态装置，具有多个状态，并且响应于其状态及其输入条件，为路由网络提供数据控制和执行非数据控制性质的多个控制功能。还提供了一种计算机，输入键盘，视听回放设备和电视机，其与寄存器和存储器装置可操作地相关联，用于向其提供输入条件并响应于其输出条件。

8. 发明授权

US3644936A Method for measuring performance of a general purpose digital computer 失效
标题翻译：用于测量一般用途数字电脑性能的方法
公开(公告)号：US3644936A
公开(公告)日：1972-02-22
申请号：US3644936D
申请日：1970-01-23
申请人： BOOLE & BABBAGE INC
发明人： HOLTWICK GARY M , KOLENCE KENNETH W
IPC分类号： G06F11/34 , G06F9/19 , G05B23/02 , G06F7/02 , G06F11/06
CPC分类号： G06F11/3423
摘要： Apparatus and method for determining how a computer program is performing by sampling the operative conditions of a number of operating elements of a computer, such as the elements of the processing unit and the memory thereof. The information obtained from such sampling can be used to establish whether the program is ''''waiting,'''' ''''executing'''' or ''''actively computing.'''' Thus, a review of this information can be used to determine if the computer is being adequately utilized by the program and, if not, how it can be more efficiently utilized. The information is extracted randomly during the execution of the program following which the information is categorized and read out so as to be in an observable form.

9. 发明授权

US4204253A Device for generating and correcting a user program 失效
标题翻译：用于生成和更正用户程序的设备
公开(公告)号：US4204253A
公开(公告)日：1980-05-20
申请号：US888506
申请日：1978-03-20
申请人： Joannes G. van den Hanenberg , Frederikus J. de Munnik
发明人： Joannes G. van den Hanenberg , Frederikus J. de Munnik
IPC分类号： G05B15/02 , G05B19/05 , G05B19/409 , G05B19/4093 , G06F3/02 , G06F9/06 , G06F9/44 , G06F15/16 , G06F9/19
CPC分类号： G06F3/0227 , G05B19/409 , G05B19/4093 , G05B2219/34215 , G05B2219/36008 , G05B2219/36043 , G05B2219/36159 , Y02P90/265 , Y10S706/908
摘要： The invention relates to a programming panel which preferably comprises a micro-processor and whereby an operator can generate or modify the contents of steps of a user program by means of a number of selection means and value input means, inter alia on the basis of indications displayed on display means for this purpose. The user program is at the disposal of a machine control system, it preferably being possible to couple the programming panel to the system by way of a bus connection. The programming panel comprises standard selection means, notably for so-termed movement primitives.
摘要翻译：本发明涉及一种编程面板，其优选地包括微处理器，由此操作者可以借助于多个选择装置和值输入装置，尤其是基于指示来产生或修改用户程序的步骤的内容为此显示在显示装置上。用户程序由机器控制系统处理，优选地可以通过总线连接将编程面板耦接到系统。编程面板包括标准选择装置，特别是用于所谓的运动原语。

10. 发明授权

US4161026A Hardware controlled transfers to microprogram control apparatus and return via microinstruction restart codes 失效
标题翻译：硬件控制传输到微程序控制装置，并通过微指令重启代码返回
公开(公告)号：US4161026A
公开(公告)日：1979-07-10
申请号：US853981
申请日：1977-11-22
申请人： John E. Wilhite
发明人： John E. Wilhite
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28 , G06F9/38 , G06F9/14 , G06F9/19 , G06F9/20 , G06F13/08
CPC分类号： G06F9/28 , G06F9/268 , G06F9/3861
摘要： A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an address field and a control sequence field for each program instruction required to be executed by the processing unit. The second control store includes a plurality of groups of storage locations, each group storing microinstructions required for executing at least a portion of at least one program instruction. Each sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which can not be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern. When decoded, the hardware sequence circuits is conditioned to enter an escape state enabling control to be transferred to a sequence specified by the address field. Instruction execution proceeds under microprogram control while the hardware sequence circuits remain in the same state. Upon the decoding of a microinstruction containing a restart field, the hardware sequence circuits are switched from the escape state to a state which enables the continuing of hardware instruction execution in a pipeline mode.
摘要翻译：微程序流水线数据处理单元包括第一控制存储器，第二控制存储器和多个硬件序列控制电路。第一控制存储器包括多个存储位置，用于存储地址字段的每个位置和用于由处理单元执行的每个程序指令的控制序列字段。第二控制存储器包括多组存储位置，每个组存储执行至少一个程序指令的至少一部分所需的微指令。每个序列包括至少一个微指令，其包含编码的重启字段，以指定硬件序列电路继续执行指令的条件。对于在流水线模式中不能由多个硬件序列电路执行的每个程序指令，控制序列字段被编码为包括预定位模式。当解码时，硬件序列电路被调节为进入转移状态，使得能够将控制转移到由地址字段指定的序列。指令执行在微程序控制下进行，而硬件序列电路保持在相同的状态。在对包含重新启动字段的微指令进行解码时，硬件序列电路从转义状态切换到能够在流水线模式下继续执行硬件指令的状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式