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1. 发明授权

US5155856A Arrangement in a self-guarding data processing system for system initialization and reset 失效
标题翻译：用于系统初始化和复位的自卫数据处理系统中的布置
公开(公告)号：US5155856A
公开(公告)日：1992-10-13
申请号：US401332
申请日：1989-08-31
申请人： Dietrich W. Bock , Peter Mannherz , Peter Rudolph , Hermann Schulze-Scholling
发明人： Dietrich W. Bock , Peter Mannherz , Peter Rudolph , Hermann Schulze-Scholling
IPC分类号： G01R31/3185 , G06F1/24 , G06F11/14
CPC分类号： G06F1/24 , G01R31/318558 , G06F11/1415
摘要： In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation, e.g., processing/logging error data, prior to a processor start. One or more reset areas are defined which are initialized/reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause, e.g., power-on, for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.
摘要翻译：在计算机系统中，代表内部处理器状态的处理器锁存器的有意识的初始化/复位是必需的，以便在处理器启动之前仅擦除后续操作（例如处理/记录错误数据）不需要的这样的信息。定义了一个或多个复位区域，这些区域以交错模式被初始化/复位，其中在每个区域中组合一组锁存器，这些锁存器必须根据原因进行初始化/复位，例如上电，用于这种系统初始化 /重启。复位区域内的锁存器被连接以形成移位寄存器，这些移位寄存器通过将要复位的区域的所有锁存器传播二进制零来初始化/复位。

2. 发明授权

US4398247A Control device for directing execution of forced operations in a data processing system 失效
标题翻译：用于在数据处理系统中指示强制操作的控制装置
公开(公告)号：US4398247A
公开(公告)日：1983-08-09
申请号：US186876
申请日：1980-09-12
申请人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
发明人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
IPC分类号： G06F9/48 , G06F9/26 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/46 , G06F9/18
CPC分类号： G06F9/3867 , G06F9/268 , G06F9/30145 , G06F9/3836
摘要： In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead.An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated.If the control signals need be grouped for physical reasons, it is possible to determine which of these signals are a function of forced operations. This will negate the need to otherwise distribute these control signals throughout the decoder, thereby reducing and simplifying the wiring required.
摘要翻译：在执行和控制特定程序的内部数据流时，通常需要通过插入适当数量的等待周期来延迟指令的执行。因此，可能需要中断指令执行，例如，将用于频道访问的给定数量的等待周期插入到数据处理系统的公共存储器中，用于重新加载数据或指令缓冲器或类似情况。在这种情况下，控制单元必须忽略等待执行的特定指令，而不是执行另一个强制操作。为NO OPERATION指令提供了一个适当的代码，比如说所有位为零。当执行强制操作时，可以在指令寄存器的输出端以较少的逻辑方式生成该代码。结果，在解码器的输出处没有控制信号有效。仅当要生成控制信号时，必须由解码器考虑指示强制操作的信号。如果控制信号由于物理原因需要分组，则可以确定这些信号中的哪一个是强制操作的功能。这将消除在整个解码器中分发这些控制信号的需要，从而减少和简化所需的布线。

3. 发明授权

US4231085A Arrangement for micro instruction control 失效
标题翻译：微指令控制安排
公开(公告)号：US4231085A
公开(公告)日：1980-10-28
申请号：US934781
申请日：1978-08-18
申请人： Dieter Bazlen , Rolf Berger , Arnold Blum , Dietrich W. Bock , Herbert Chilinski , Hellmuth R. Geng , Johann Hajdu , Fritz Irro , Siegfried Neuber , Udo Wille
发明人： Dieter Bazlen , Rolf Berger , Arnold Blum , Dietrich W. Bock , Herbert Chilinski , Hellmuth R. Geng , Johann Hajdu , Fritz Irro , Siegfried Neuber , Udo Wille
IPC分类号： G06F9/22 , G06F9/12
CPC分类号： G06F9/226
摘要： In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.
摘要翻译：在微控制数据处理系统中，通过使用两个总线路径来将控制信号从微程序控制传送到由这些信号控制的集成电路模块所需的线和引脚的数量被保存，用于将控制信号分配到模块。专用于预解码控制信号功能的第一路径，并且共享用于传送数据和控制信号功能的第二路径。每个受控模块包括用于组合地解码通过两条路径接收的控制信号功能的附加解码电路。

4. 发明授权

US4400776A Data processor control subsystem 失效
标题翻译：数据处理器控制子系统
公开(公告)号：US4400776A
公开(公告)日：1983-08-23
申请号：US186883
申请日：1980-09-12
申请人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
发明人： Dieter Bazlen , Dietrich W. Bock , Klaus J. Getzlaff , Johann Hajdu , Helmut Painke
IPC分类号： G06F1/04 , G06F9/22 , G06F9/26 , G06F9/30 , G06F9/302 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3001 , G06F9/223 , G06F9/26 , G06F9/3869
摘要： An improved data processor control subsystem in which a cycle counter having a plurality of cascade-connected stages also comprises one or more supplemental or dummy stages, which can be selectively inserted or removed from the chain of cascade-connected stages, to alter the number of sub-cycles in an operating cycle, thereby decreasing the complexity of associated decoding circuitry.
摘要翻译：一种改进的数据处理器控制子系统，其中具有多个级联连接级的循环计数器还包括一个或多个补充或虚拟级，其可以从级联连接级链中选择性地插入或移除，以改变子周期，从而降低相关解码电路的复杂度。

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