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1. 发明授权

US5319948A Low temperature generation process and expansion engine 失效
标题翻译：低温发电过程和膨胀发动机
公开(公告)号：US5319948A
公开(公告)日：1994-06-14
申请号：US876273
申请日：1992-04-30
申请人： Arnold Blum , Manfred Schmidt
发明人： Arnold Blum , Manfred Schmidt
IPC分类号： F25B9/00 , F03G7/00 , F25B9/06 , F25B9/14
CPC分类号： F03G7/002 , F25B9/065 , F25B9/145 , F02G2243/52 , F25B2309/1402 , F25B2309/1408 , F25B2309/1425
摘要： In a low temperature generation process, compressed gas (3) at high pressure enters from an inlet nozzle (1) and alternately expands into one of two resonator tubes (A,B) of an expansion engine. The expanding gas excites standing acoustic waves (4) in the resonator tubes (A,B). The acoustic energy of the waves (4) is converted into electrical energy by acoustic/electric power converters and is led away outside the "cold area" of the tubes. The expansion engine contains one or more resonator tubes with a common inlet nozzle (1). Each resonator tube has an acoustic/electric power converter (5) and an exhaust port (6). Together with a compressor, a heat exchanger and a heat sink, the expansion engine provides a very effective cooling system which may be used for the cooling of small electronic devices like chips or modules.
摘要翻译：在低温发生过程中，高压下的压缩气体（3）从入口喷嘴（1）进入并交替地膨胀成膨胀发动机的两个谐振管（A，B）之一。膨胀气体激励谐振器管（A，B）中的驻波（4）。波浪（4）的声能通过声/电功率转换器转换成电能，并被引导到管的“冷区”之外。膨胀发动机包含一个或多个具有公共入口喷嘴（1）的谐振管。每个谐振器管具有声/电功率转换器（5）和排气口（6）。与压缩机，热交换器和散热器一起，膨胀发动机提供了非常有效的冷却系统，其可用于冷却诸如芯片或模块的小型电子设备。

2. 发明授权

US4688222A Built-in parallel testing circuit for use in a processor 失效
标题翻译：内置并行测试电路，用于处理器
公开(公告)号：US4688222A
公开(公告)日：1987-08-18
申请号：US810105
申请日：1985-12-17
申请人： Arnold Blum
发明人： Arnold Blum
IPC分类号： G06F11/22 , G06F11/27 , G01R31/28
CPC分类号： G06F11/27
摘要： The invention concerns arrangements and methods for error testing and diagnosing processors (e.g., 9; FIG. 2), whose logic subsystems (20) are interconnected by storage elements (23, 24) which in the error test and diagnostic mode are connected in the form of shift register means for the shift clock controlled application of test data and for receiving result data, and which comprise means (58) for comparing the actual result data with desired result data, said means setting an error indicator (59) for initiating further actions in the case of a mismatch. For testing the correct implementation of operations and operational secondary functions, a signature generator circuit (30) is provided comprising a test accumulator (51, 52, . . . , 5m) for accumulating the test and result data from the storage elements (23, 24) and a test clock generator and counter (28) for controlling the accumulation, as well as a test memory (29) providing test programs consisting of test data, desired result data and instructions to be tested of the processor instruction set. The signature generator circuit ( 30) is connected to an interface register (11, 12, . . . , 1m) and/or a system bus (8) of the processor, the stages of the interface register being included in the shift register means consisting of the storage elements (23, 24) at positions 21, 22, . . . , nm.
摘要翻译：本发明涉及用于对其逻辑子系统（20）由存储元件（23,24）进行互连的处理器（例如，9;图2）进行错误测试和诊断的布置和方法，所述存储元件在故障测试和诊断模式中被连接在用于移位时钟控制应用测试数据和接收结果数据的移位寄存器装置的形式，其包括用于将实际结果数据与期望结果数据进行比较的装置（58），所述装置设置用于进一步发起的错误指示符（59）在不匹配的情况下的行为。为了测试操作和操作次要功能的正确实现，提供了一种签名生成器电路（30），其包括用于累积来自存储元件（23,23）的测试和结果数据的测试累加器（51,52 ...，5m） 24）和用于控制累积的测试时钟发生器和计数器（28）以及提供由测试数据，期望结果数据和待处理指令集的指令组成的测试程序的测试存储器（29）。签名生成器电路（30）连接到处理器的接口寄存器（11,12，...，1m）和/或系统总线（8），接口寄存器的级包括在移位寄存器装置由位置21,22上的存储元件（23,24）组成。。。，nm。

3. 发明授权

US4030076A Processor nucleus combined with nucleus time controlled external registers integrated with logic and arithmetic circuits shared between nucleus and I/O devices 失效
标题翻译：处理器核与核时间控制的外部寄存器结合，与核和I / O设备之间共享的逻辑和运算电路集成
公开(公告)号：US4030076A
公开(公告)日：1977-06-14
申请号：US596487
申请日：1975-07-16
申请人： Arnold Blum , Johann Hajdu , Claus Erich Mohr , Leopold Reichl , Guenther Sonntag
发明人： Arnold Blum , Johann Hajdu , Claus Erich Mohr , Leopold Reichl , Guenther Sonntag
IPC分类号： G06F9/22 , G06F13/12 , G06F13/14 , G06F15/16 , G06F15/78 , G06F3/00 , G06F7/38 , G06F9/12
CPC分类号： G06F13/122 , G06F13/124 , G06F15/7832 , G06F15/7864 , G06F9/226
摘要： Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.
摘要翻译：与逻辑和运算电路集成的输入/输出寄存器在仅具有存储寄存器，指令解码逻辑，定时电路和算术和逻辑单元的处理器核的外部组合，用于执行微指令，从而使用输入/输出寄存器由微程序代码并且通过时间控制来选择性地执行用于输入和输出设备的所有适配器和接口通信和控制功能，或者选择性地切换到处理器核的数据流。

4. 发明授权

US5164818A Removable VLSI assembly 失效
标题翻译：可拆卸的VLSI总成
公开(公告)号：US5164818A
公开(公告)日：1992-11-17
申请号：US765072
申请日：1991-09-24
申请人： Arnold Blum , Frank Gerth , Manfred Perske , Manfred Schmidt
发明人： Arnold Blum , Frank Gerth , Manfred Perske , Manfred Schmidt
IPC分类号： H01L23/12 , H01L23/48 , H01L23/50 , H01R4/02 , H01R4/24 , H05K1/18 , H05K3/28 , H05K3/30 , H05K3/32 , H05K3/34
CPC分类号： H01L23/48 , H05K3/306 , H05K3/32 , H01L2924/0002 , H05K2201/09472 , H05K2201/10575 , H05K2201/10689 , H05K2201/10704 , H05K2203/0285 , H05K2203/1189 , H05K2203/176 , H05K3/281 , H05K3/3463
摘要： A system for mounting VLSI devices on a substrate is disclosed, offering a high contact density. Each package consists of a semiconductor device having protruding elongated contact pin (2) on its surface and a wiring substrate having a cavity (3) on its surface. The cavities are filed with a conductive material (7) of a low melting point composition and sealed with a thin non-conductive foil (4). During packaging, the contact pins are made to penetrate the foil, and extend into the conductive alloy, thus making electrical contact therewith. To ease the penetration of the foil, the contact pins could be set into oscillating motion by means of an ultrasonic generator.

5. 发明授权

US4295220A Clock check circuits using delayed signals 失效
标题翻译：使用延迟信号的时钟检查电路
公开(公告)号：US4295220A
公开(公告)日：1981-10-13
申请号：US98587
申请日：1979-11-29
申请人： Arnold Blum , Hellmuth R. Geng , Hermann Schulze-Schoelling , Bernd Spaeth
发明人： Arnold Blum , Hellmuth R. Geng , Hermann Schulze-Schoelling , Bernd Spaeth
IPC分类号： G01R31/28 , G01R31/3183 , G04D7/00 , H03K5/26 , H04M3/24 , H03K5/19 , G06F1/04
CPC分类号： H04M3/24 , H03K5/26
摘要： In a data processing or transmission system which includes at least two synchronized clocks, for example--T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock.Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
摘要翻译：在包括至少两个同步时钟的数据处理或传输系统中，例如T形环A和B，其产生用于微指令执行的定时脉冲Tai和Tbi，由从时钟接收脉冲的逻辑电路来检查同步。至少一个脉冲被延迟一个或多个脉冲周期持续时间ti。逻辑电路输出信号用作由独立的检查振荡器或时钟周期性地设置的指示器锁存器的输入。在优选实施例中，延迟由主 - 从触发器引入，主 - 从触发器接收T信号的预定组合并由独立检查时钟设置。延迟锁存器和关联的与门可以用于延迟和未延迟T信号的不同逻辑组合。该方案可以轻松扩展，以容纳两个以上的同步操作时钟。这些电路不仅检查时钟的瞬时同步，还检查时钟脉冲的正确排序。如果每个微指令执行的T形环计数器以可变数量的时钟脉冲操作，则该检查也是可行的。

6. 发明授权

US5467452A Routing control information via a bus selectively controls whether data should be routed through a switch or a bus according to number of destination processors 失效
标题翻译：通过总线的路由控制信息选择性地控制数据是否应该根据目标处理器的数目通过交换机或总线路由
公开(公告)号：US5467452A
公开(公告)日：1995-11-14
申请号：US91706
申请日：1993-07-14
申请人： Arnold Blum , Gottfried Goldrian , Wolfgang Kumpf
发明人： Arnold Blum , Gottfried Goldrian , Wolfgang Kumpf
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F13/12 , G06F13/14
CPC分类号： G06F15/17375
摘要： The invention concerns the transfer of data information in a multiprocessor computer system. If data information has to be transferred between two processor units then the associated control information is made available on a connection bus and the data information is transferred afterwards via a switch unit from the first to the second processor unit. If however data information is to be transferred from a sending processor unit to all other processor units (broadcast transfer) then not only is control information transferred via the connection bus but subsequent data information too; a transfer of data information via the switch unit does not occur in this case. In this manner it is possible to reduce the outlay for the switch unit in terms of circuitry and programming.
摘要翻译：本发明涉及在多处理器计算机系统中传送数据信息。如果数据信息必须在两个处理器单元之间传送，则相关联的控制信息在连接总线上可用，并且数据信息随后经由交换单元从第一处理器单元传送到第二处理器单元。然而，如果将数据信息从发送处理器单元传送到所有其他处理器单元（广播传送），则不仅控制信息经由连接总线传送，而且也是随后的数据信息; 在这种情况下不会发生经由开关单元的数据信息的传送。以这种方式，可以减少开关单元在电路和编程方面的支出。

7. 发明授权

US5078581A Cascade compressor 失效
标题翻译： CASCADE压缩机
公开(公告)号：US5078581A
公开(公告)日：1992-01-07
申请号：US562302
申请日：1990-08-03
申请人： Arnold Blum , Manfred Perske , Manfred Schmidt
发明人： Arnold Blum , Manfred Perske , Manfred Schmidt
IPC分类号： F04B43/04 , F04B45/04 , F04B45/047
CPC分类号： F04B43/043 , F04B45/041 , F04B45/047
摘要： The compressor cascade comprises a plurality of tandem-connected membrane pumps, each of the pumps having a plurality of stroke chambers whose volumes decrease in the direction of the fluid flow through the pumps. Each chamber has several parallel-connected input/output channels for interconnecting the individual membrane pumps and a check valve in each input/output channel for forcing the fluid in a specified direction. By electrostatic attraction forces, the membranes in the pumps are energized synchronously to resonance oscillations of the same frequency and deflection, building up the necessary operating pressure as the fluid is moved from the stroke chamber of one membrane pump into the smaller volume stroke chamber of the next succeeding membrane pump. The movement of the fluid through the membrane pumps of the compressor cascade leads to its compression, and the pressure at the end of the cascade is related to the reduction in volume of each succeeding stroke chamber.

8. 发明授权

US4669079A Method and apparatus for bus arbitration in a data processing system 失效
标题翻译：数据处理系统中总线仲裁的方法和装置
公开(公告)号：US4669079A
公开(公告)日：1987-05-26
申请号：US789985
申请日：1985-10-22
申请人： Arnold Blum
发明人： Arnold Blum
IPC分类号： G06F13/362 , G06F13/364 , G06F15/16 , G06F15/177 , H04J3/02
CPC分类号： G06F13/364
摘要： In a bus-oriented computer system, the decision as to which unit is to receive the bus takes account of the current status of the bus system and the respective operation to be performed on the bus. For that purpose, status information of the connected units, the bus command to be executed and the address of the requested unit are fed to the allocation logic (arbiter) on separate or commonly used lines, thus avoiding idle times during the use of the bus. By evaluating the bus command, the allocation priority can be dynamically changes in order to suppress bus accesses that are bound to fail from the start.
摘要翻译：在面向总线的计算机系统中，关于哪个单元接收总线的决定考虑到总线系统的当前状态以及要在总线上执行的相应操作。为此，连接的单元的状态信息，要执行的总线命令和请求的单元的地址在单独的或常用的线路上馈送到分配逻辑（仲裁器），从而避免在使用总线期间的空闲时间。通过评估总线命令，可以动态地改变分配优先级，以便抑制从一开始就绑定失败的总线访问。

9. 发明授权

US4604746A Testing and diagnostic device for digital computers 失效
标题翻译：数字电脑测试和诊断设备
公开(公告)号：US4604746A
公开(公告)日：1986-08-05
申请号：US602108
申请日：1984-04-19
申请人： Arnold Blum
发明人： Arnold Blum
IPC分类号： G06F11/22 , G06F11/273
CPC分类号： G06F11/2736
摘要： For error testing and diagnostics in EDP systems, particular storage elements (e.g., 6) are connected to form an addressable matrix which is coupled to a maintenance and service processor (5) or an external tester through the system bus (9). During normal operation, the logic subsystems (10), of which processors (1) and processing units consist, are connected by the storage elements. Through the system bus, the maintenance and service processor or the tester transfers addresses to the matrix and test data to the addressed storage elements from where they are fed to the logic subsystems which in turn respond to such test data, transferring the (partial) result data thus received to the storage elements. In the next step, the maintenance and service processor or the external tester causes the result data for error analysis and diagnostics to be fetched through the system bus from the storage elements reconnected in the form of a matrix.
摘要翻译：对于EDP系统中的错误测试和诊断，特定存储元件（例如6）被连接以形成可寻址矩阵，其通过系统总线（9）耦合到维护和服务处理器（5）或外部测试器。在正常操作期间，由存储元件连接处理器（1）和处理单元组成的逻辑子系统（10）。通过系统总线，维护和服务处理器或测试者将地址传送到矩阵，并将数据测试到所寻址的存储元件，从那里它们被馈送到逻辑子系统，逻辑子系统又响应于这样的测试数据，传送（部分）结果因此将数据接收到存储元件。在下一步中，维护和维修处理器或外部测试仪通过系统总线从矩阵形式重新连接的存储元件中取出用于错误分析和诊断的结果数据。

10. 发明授权

US4490673A Testing an integrated circuit containing a tristate driver and a control signal generating network therefor 失效
标题翻译：测试包含三态驱动器和控制信号生成网络的集成电路
公开(公告)号：US4490673A
公开(公告)日：1984-12-25
申请号：US382267
申请日：1982-05-26
申请人： Arnold Blum , Helmut Schettler
发明人： Arnold Blum , Helmut Schettler
IPC分类号： H03K19/00 , G01R31/316 , G01R31/317 , G01R31/319 , H03K19/0175 , G01R31/00 , G01R31/26
CPC分类号： G01R31/316
摘要： An integrated circuit chip includes a tristate driver which assumes an active logical state in response to a data signal at its data input and assumes a high impedance state in response to a control signal at its control input. The integrated circuit chip also includes a control signal generating network which is connected to the tristate driver's control input for producing the control signal. The control signal generating network may be tested by connecting the control signal generating network to the data input and overriding the control input to prevent the tristate driver from assuming the high impedance state. Thus, for testing purposes, the proper response of the control signal generating circuit may be ascertained by monitoring the active state of the tristate driver.
摘要翻译：集成电路芯片包括三态驱动器，其响应于其数据输入处的数据信号而呈现有效逻辑状态，并且响应于其控制输入处的控制信号而呈现高阻抗状态。集成电路芯片还包括控制信号生成网络，其连接到三态驱动器的控制输入端以产生控制信号。可以通过将控制信号生成网络连接到数据输入并覆盖控制输入来防止三态驱动器呈现高阻抗状态来测试控制信号生成网络。因此，为了测试目的，可以通过监视三态驱动器的活动状态来确定控制信号发生电路的适当响应。

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