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1. 发明授权

US08375347B2 Driven metal critical dimension (CD) biasing 有权
标题翻译：驱动金属临界尺寸（CD）偏置
公开(公告)号：US08375347B2
公开(公告)日：2013-02-12
申请号：US12464578
申请日：2009-05-12
申请人： Louis Chao-Chiuan Liu , Lee-Chung Lu , Yao-Ching Ku
发明人： Louis Chao-Chiuan Liu , Lee-Chung Lu , Yao-Ching Ku
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5031 , G06F17/5036 , G06F17/5077 , G06F2217/84
摘要： A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.
摘要翻译：提供了一种设计集成电路（IC）的方法，其包括放置IC设计，其中IC设计包括第一元件，第二元件以及耦合第一和第二元件的路径，以及布线IC设计。此外，该方法包括获得与路径相关的电阻率数据和电容数据中的至少一个，并获得与该路径相关的定时数据。该方法还包括使用电阻率数据，电容数据和定时数据中的至少一个来确定要施加到路径的临界尺寸（CD）偏置，以及修改IC设计，其中修改包括应用CD偏差到路上

2. 发明申请

US20110231804A1 MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION 有权
标题翻译：电子设计自动化模型进口
公开(公告)号：US20110231804A1
公开(公告)日：2011-09-22
申请号：US13116981
申请日：2011-05-26
申请人： Ru-Gun Liu , Chih-Ming Lai , Wen-Chun Huang , Boren Luo , I-Chang Shin , Yao-Ching Ku , Cliff Hou
发明人： Ru-Gun Liu , Chih-Ming Lai , Wen-Chun Huang , Boren Luo , I-Chang Shin , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.
摘要翻译：公开了以安全格式提供处理参数的方法和系统。一方面，公开了一种向设计设备提供半导体制造处理参数的方法。该方法包括提供制造设施的一组处理参数; 从一组处理参数创建模型; 将模型转换为相应的一组内核; 将所述内核集合转换成相应的矩阵集合; 并将该组矩阵传送到设计设施。另一方面，公开了一种用于提供半导体制造处理参数的方法。该方法包括提供制造设施的一组处理参数; 从一组处理参数创建一个处理模型; 将处理模型加密成与多个EDA工具一起使用的格式; 并将加密的处理模型格式传送到设计设施。

3. 发明授权

US07778805B2 Regression system and methods for optical proximity correction modeling 有权
标题翻译：用于光学邻近校正建模的回归系统和方法
公开(公告)号：US07778805B2
公开(公告)日：2010-08-17
申请号：US11191849
申请日：2005-07-28
申请人： Wen Chun Huang , Ru-Gun Liu , Chih-Ming Lai , Chen Kun Tsai , Chien Wen Lai , Cherng-Shyan Tsay , Cheng Cheng Kuo , Yao-Ching Ku
发明人： Wen Chun Huang , Ru-Gun Liu , Chih-Ming Lai , Chen Kun Tsai , Chien Wen Lai , Cherng-Shyan Tsay , Cheng Cheng Kuo , Yao-Ching Ku
IPC分类号： G06F7/60 , G06F17/10
CPC分类号： G03F1/36 , G03F1/68
摘要： An optimized optical proximity correction modeling method comprises receiving a selection of a regression method, displaying regression parameters, receiving values for the displayed regression parameters, receiving a selection of an optimization method, displaying optimization parameters, receiving values for the displayed optimization parameters, and generating an optimized optical proximity correction output.
摘要翻译：优化的光学邻近校正建模方法包括接收回归方法的选择，显示回归参数，接收显示的回归参数的值，接收优化方法的选择，显示优化参数，接收显示的优化参数的值，以及生成优化的光学邻近校正输出。

4. 发明申请

US20100095253A1 TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS 有权
标题翻译：基于表的DFM用于精确的后布局分析
公开(公告)号：US20100095253A1
公开(公告)日：2010-04-15
申请号：US12250424
申请日：2008-10-13
申请人： Yung-Chin HOU , Ying-Chou CHENG , Ru-Gun LIU , Chih-Ming LAI , Yi-Kan CHENG , Chung-Kai LIN , Hsiao-Shu CHAO , Ping-Heng YEH , Min-Hong WU , Yao-Ching KU , Tsong-Hua OU
发明人： Yung-Chin HOU , Ying-Chou CHENG , Ru-Gun LIU , Chih-Ming LAI , Yi-Kan CHENG , Chung-Kai LIN , Hsiao-Shu CHAO , Ping-Heng YEH , Min-Hong WU , Yao-Ching KU , Tsong-Hua OU
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

5. 发明授权

US07387969B2 Top patterned hardmask and method for patterning 有权
标题翻译：顶部图案化硬掩模和图案化方法
公开(公告)号：US07387969B2
公开(公告)日：2008-06-17
申请号：US11084495
申请日：2005-03-18
申请人： George Liu , Vencent Chang , Norman Chen , Yao-Ching Ku , Chin-Hsiang Lin , Kuei Shun Chen
发明人： George Liu , Vencent Chang , Norman Chen , Yao-Ching Ku , Chin-Hsiang Lin , Kuei Shun Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , G03F7/11 , H01L21/0274 , H01L21/0332 , H01L21/76807
摘要： A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.
摘要翻译：一种图案化硬掩模及其形成方法，所述方法包括提供包含对活化辐射敏感的上覆抗蚀剂的基底; 形成对激活辐射不敏感的上覆硬掩模; 将抗蚀剂通过硬掩模暴露于活化辐射; 烘烤抗蚀剂和硬掩模; 并开发硬掩模和抗蚀剂以形成图案化的抗蚀剂和图案化的硬掩模。

6. 发明申请

US20050195397A1 In-situ overlay alignment 有权
标题翻译：原位重叠对齐
公开(公告)号：US20050195397A1
公开(公告)日：2005-09-08
申请号：US10792147
申请日：2004-03-03
申请人： Grace Ho , Ming-Che Wu , Li-Heng Chou , Hung-Chang Hsieh , Jung Chen , Yao-Ching Ku
发明人： Grace Ho , Ming-Che Wu , Li-Heng Chou , Hung-Chang Hsieh , Jung Chen , Yao-Ching Ku
IPC分类号： G01B11/00 , G03F9/00
CPC分类号： G03F9/7084 , G03F7/70633
摘要： A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.
摘要翻译：公开了一种半导体晶片，其包括多个场，包括多个对准场。每个对准场包括在其周围的多个场内小划线通道主标记（SSPM）覆盖标记对。 SSPM标记对允许原位，非被动场内对准校正。在一个实施例中，可以在两个和四个对准场之间以及围绕每个对准场的两个和四个SSPM标记对之间。每个标记对的SSPM标记可能是额外的划线标记。

7. 发明申请

US20050023463A1 CD sem automatic focus methodology and apparatus for constant electron beam dosage control 有权
标题翻译： CD半自动聚焦方法和恒电子束剂量控制装置
公开(公告)号：US20050023463A1
公开(公告)日：2005-02-03
申请号：US10628914
申请日：2003-07-29
申请人： Chih-Ming Ke , Chien-Hsun Lin , Yao-Ching Ku
发明人： Chih-Ming Ke , Chien-Hsun Lin , Yao-Ching Ku
IPC分类号： G01N23/225
CPC分类号： G01N23/2251
摘要： Reducing photoresist shrinkage by plasma treatment is disclosed. A semiconductor wafer having one or more photoresist layers is plasma treated, such as plasma curing, plasma etching, and/or high-density plasma etching the wafer. After plasma treating, one or more critical dimensions on the photoresist layers is measured using an electron beam, such as by using a scanning electron microscope (SEM). The plasma treating of the wafer prior to measuring the critical dimensions using the electron beam decreases shrinkage of the photoresist layer when using the electron beam.
摘要翻译：公开了通过等离子体处理降低光刻胶的收缩率。具有一个或多个光致抗蚀剂层的半导体晶片被等离子体处理，例如等离子体固化，等离子体蚀刻和/或高密度等离子体蚀刻晶片。在等离子体处理之后，使用电子束，例如通过使用扫描电子显微镜（SEM）测量光致抗蚀剂层上的一个或多个临界尺寸。在使用电子束测量临界尺寸之前对晶片的等离子体处理降低了当使用电子束时光致抗蚀剂层的收缩。

8. 发明授权

US06291112B1 Method of automatically forming a rim phase shifting mask 有权
标题翻译：自动形成轮辋相移掩模的方法
公开(公告)号：US06291112B1
公开(公告)日：2001-09-18
申请号：US09191762
申请日：1998-11-13
申请人： Chin-Lung Lin , Yao-Ching Ku
发明人： Chin-Lung Lin , Yao-Ching Ku
IPC分类号： G03F900
CPC分类号： G03F1/29
摘要： A method of automatically forming a rim PSM is provided. A first pattern comprising a conventional original pattern as a blinding layer and assist features around the conventional circuit pattern is designed. A portion of a Cr film and a portion of a phase shifting layer under the Cr film are removed with the first pattern. The removed portion of the Cr film and the removed portion of the phase shifting layer are positioned on the assist feature. A second pattern comprising the conventional circuit pattern and a half of the assist features is designed. A portion of the Cr film in positions other than on the second pattern is removed. The convention circuit pattern formed at the mask medium is defined as the blinding layer. The area of the assist features only comprise a quartz substrate that light can pass through. The other areas of the mask medium wherein the phase shifting layer remains is defined as the phase-shifting portion of the PSM.
摘要翻译：提供了一种自动形成边缘PSM的方法。设计了包括常规原始图案作为盲目层并且围绕常规电路图案的辅助特征的第一图案。利用第一图案除去Cr膜的一部分和在Cr膜下面的部分相移层。 Cr膜的去除部分和移相层的去除部分位于辅助特征上。设计包括常规电路图案和辅助特征的一半的第二图案。除去在第二图案之外的位置中的Cr膜的一部分。形成在掩模介质上的常规电路图形被定义为盲目层。辅助特征的区域仅包括光可以通过的石英衬底。其中相移层保留的掩模介质的其它区域被定义为PSM的相移部分。

9. 发明授权

US06251564B1 Method for forming a pattern with both logic-type and memory-type circuit 有权
标题翻译：用逻辑型和存储型电路形成图案的方法
公开(公告)号：US06251564B1
公开(公告)日：2001-06-26
申请号：US09312968
申请日：1999-05-17
申请人： Chin-Lung Lin , Yao-Ching Ku
发明人： Chin-Lung Lin , Yao-Ching Ku
IPC分类号： G03C500
CPC分类号： G03F7/70466 , G03F7/203
摘要： A method for forming a pattern with both a logic-type and, a memory-type circuit is disclosed. The method includes first providing a wafer which includes a photoresist layer, then covering the photoresist layer with a first mask including an opaque area and a first pattern area. Forming a first pattern on the photoresist layer by a first exposure. Covering the photoresist layer with a second mask after the first mask is removed. Moreover, a second pattern is printed on the photoresist layer by a second exposure. Finally, the second mask is removed. The double-exposure method will enhance the resolution of the pattern defined on the photoresist layer.
摘要翻译：公开了一种用于形成具有逻辑类型和存储器型电路的图案的方法。该方法包括首先提供包括光致抗蚀剂层的晶片，然后用包括不透明区域和第一图案区域的第一掩模覆盖光致抗蚀剂层。通过第一次曝光在光致抗蚀剂层上形成第一图案。在去除第一掩模之后用第二掩模覆盖光致抗蚀剂层。此外，通过第二曝光将第二图案印刷在光致抗蚀剂层上。最后，删除第二个掩码。双曝光方法将增强在光致抗蚀剂层上限定的图案的分辨率。

10. 发明授权

US08431291B2 Intensity selective exposure photomask 有权
标题翻译：强度选择性曝光光掩模
公开(公告)号：US08431291B2
公开(公告)日：2013-04-30
申请号：US13281198
申请日：2011-10-25
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC分类号： G03F1/00 , G03F1/36
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
摘要翻译：还提供强度选择性曝光光掩模，还描述为渐变光掩模。光掩模包括包括第一子分解特征阵列的第一区域。第一个区域阻止了第一个入射辐射的百分比。光掩模还包括包括第二子分辨率特征阵列的第二区域。第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。

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