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1. 发明授权

US09367655B2 Topography-aware lithography pattern check 有权
标题翻译：地形感知光刻图案检查
公开(公告)号：US09367655B2
公开(公告)日：2016-06-14
申请号：US13443568
申请日：2012-04-10
申请人： I-Chang Shih , Chung-min Fu , Ying-Chou Cheng , Yung-Fong Lu , Feng-Yuan Chiu , Chiu Hsiu Chen
发明人： I-Chang Shih , Chung-min Fu , Ying-Chou Cheng , Yung-Fong Lu , Feng-Yuan Chiu , Chiu Hsiu Chen
IPC分类号： H01L21/66 , G06F17/50 , G03F7/20
CPC分类号： G06F17/5027 , G03F7/705 , H01L22/10 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.
摘要翻译：本公开提供了一种方法。该方法包括获得集成电路（IC）布局。该方法包括提供抛光过程模拟模型。该方法包括对IC布局执行光刻图案校验（LPC）处理。 LPC处理至少部分地使用抛光工艺模拟模型进行。该方法包括响应于LPC过程检测IC布局上的可能问题区域。该方法包括修改抛光过程仿真模型。该方法包括重复执行LPC处理和使用改进的抛光处理模拟模型来检测可能的问题区域。

2. 发明申请

US20130267047A1 Topography-Aware Lithography Pattern Check 有权
标题翻译：地形感知光刻图案检查
公开(公告)号：US20130267047A1
公开(公告)日：2013-10-10
申请号：US13443568
申请日：2012-04-10
申请人： I-Chang Shih , Chung-min Fu , Ying-Chou Cheng , Yung-Fong Lu , Feng-Yuan Chiu , Chiu Hsiu Chen
发明人： I-Chang Shih , Chung-min Fu , Ying-Chou Cheng , Yung-Fong Lu , Feng-Yuan Chiu , Chiu Hsiu Chen
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： G06F17/5027 , G03F7/705 , H01L22/10 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.
摘要翻译：本公开提供了一种方法。该方法包括获得集成电路（IC）布局。该方法包括提供抛光过程模拟模型。该方法包括对IC布局执行光刻图案校验（LPC）处理。 LPC处理至少部分地使用抛光工艺模拟模型进行。该方法包括响应于LPC过程检测IC布局上的可能问题区域。该方法包括修改抛光过程仿真模型。该方法包括重复执行LPC处理和使用改进的抛光处理模拟模型来检测可能的问题区域。

3. 发明授权

US08527918B2 Target-based thermal design using dummy insertion for semiconductor devices 有权
标题翻译：基于目标的热设计，使用半导体器件的虚拟插入
公开(公告)号：US08527918B2
公开(公告)日：2013-09-03
申请号：US13227118
申请日：2011-09-07
申请人： Ying-Chou Cheng , Boren Luo , Wen-Hao Liu , Tsong-Hua Ou , Chih-Wei Hsu , Wen-Chun Huang , Ru-Gun Liu
发明人： Ying-Chou Cheng , Boren Luo , Wen-Hao Liu , Tsong-Hua Ou , Chih-Wei Hsu , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , G06F2217/80 , Y02P90/265
摘要： The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout.
摘要翻译：本公开提供了用于基于目标的虚拟插入的集成电路方法。一种方法包括提供集成电路（IC）设计布局，并提供用于模拟IC设计布局热效应的热模型，热模型包括光学仿真和硅校准。该方法还包括提供热模型和IC设计布局的卷积以产生IC设计布局的热图像轮廓，定义用于优化热图像轮廓的热均匀性的热目标，比较热目标和热图像以确定差异数据，并且基于差异数据对IC设计布局进行热假插入以提供基于目标的IC设计布局。

4. 发明授权

US08431291B2 Intensity selective exposure photomask 有权
标题翻译：强度选择性曝光光掩模
公开(公告)号：US08431291B2
公开(公告)日：2013-04-30
申请号：US13281198
申请日：2011-10-25
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC分类号： G03F1/00 , G03F1/36
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
摘要翻译：还提供强度选择性曝光光掩模，还描述为渐变光掩模。光掩模包括包括第一子分解特征阵列的第一区域。第一个区域阻止了第一个入射辐射的百分比。光掩模还包括包括第二子分辨率特征阵列的第二区域。第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。

5. 发明授权

US08332797B2 Parameterized dummy cell insertion for process enhancement 有权
标题翻译：用于过程增强的参数化虚拟单元插入
公开(公告)号：US08332797B2
公开(公告)日：2012-12-11
申请号：US12959150
申请日：2010-12-02
申请人： Ying-Chou Cheng , Tsong-Hua Ou , Wen-Hao Liu , Ru-Gun Liu , Wen-Chun Huang
发明人： Ying-Chou Cheng , Tsong-Hua Ou , Wen-Hao Liu , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , G06F2217/80 , Y02P90/265
摘要： The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.
摘要翻译：本公开涉及用于过程增强的参数化虚拟单元插入及其制造方法。根据一个或多个实施例，方法包括提供具有定义的像素单元的集成电路（IC）设计布局，模拟包括每个像素单元的IC设计布局的热效应，生成IC设计布局的热效应图，包括每个像素单元，确定IC设计布局的目标吸收值，并且基于所确定的目标吸收值，向IC设计布局的每个像素单元执行热虚拟单元插入。

6. 发明申请

US20110289466A1 Table-Based DFM for Accurate Post-Layout Analysis 有权
标题翻译：基于表的DFM，用于精确的后期布局分析
公开(公告)号：US20110289466A1
公开(公告)日：2011-11-24
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

7. 发明授权

US08037575B2 Method for shape and timing equivalent dimension extraction 有权
标题翻译：形状和时间等值尺寸提取方法
公开(公告)号：US08037575B2
公开(公告)日：2011-10-18
申请号：US12211624
申请日：2008-09-16
申请人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
发明人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265 , Y10T16/2771
摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
摘要翻译：集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

8. 发明申请

US20110124193A1 CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION 有权
标题翻译：自定义模式调整和优化
公开(公告)号：US20110124193A1
公开(公告)日：2011-05-26
申请号：US12625749
申请日：2009-11-25
申请人： Ying-Chou Cheng , Ru-Gun Liu , Josh J.H. Feng , Tsong-Hua Ou , Luke Lo , Chih-Ming Lai , Wen-Chun Huang
发明人： Ying-Chou Cheng , Ru-Gun Liu , Josh J.H. Feng , Tsong-Hua Ou , Luke Lo , Chih-Ming Lai , Wen-Chun Huang
IPC分类号： H01L21/033 , G06F17/50
CPC分类号： G06F17/5068
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.
摘要翻译：本公开提供了集成电路（IC）设计方法的一个实施例。该方法包括提供电路的IC设计布局; 根据电路的电气参数和IC设计布局的光学参数，对IC设计布局进行电气图案化（ePatterning）修改; 然后根据IC设计布局制造掩模。

9. 发明申请

US20090222785A1 METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION 有权
标题翻译：形状和时间等效尺寸提取方法
公开(公告)号：US20090222785A1
公开(公告)日：2009-09-03
申请号：US12211624
申请日：2008-09-16
申请人： Ying-Chou CHENG , Chih-Ming LAI , Ru-Gun LIU , Tsong-Hua OU , Min-Hong WU , Yih-Yuh DOONG , Hsiao-Shu CHAO , Yi-Kan CHENG , Yao-Ching KU , Cliff HOU
发明人： Ying-Chou CHENG , Chih-Ming LAI , Ru-Gun LIU , Tsong-Hua OU , Min-Hong WU , Yih-Yuh DOONG , Hsiao-Shu CHAO , Yi-Kan CHENG , Yao-Ching KU , Cliff HOU
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265 , Y10T16/2771
摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
摘要翻译：集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

10. 发明授权

US06486463B1 Computer input device with encoders having flexible shafts and conical rollers 失效
标题翻译：具有编码器的计算机输入设备，具有柔性轴和圆锥滚子
公开(公告)号：US06486463B1
公开(公告)日：2002-11-26
申请号：US09480323
申请日：2000-01-10
申请人： Marc A. Bidiville , Ying Chou Cheng
发明人： Marc A. Bidiville , Ying Chou Cheng
IPC分类号： G06M700
CPC分类号： G06F3/03543 , G06F3/0312
摘要： A method and apparatus for replacing two separate photo detectors chips and two photo emitters by a single photo detector chip and a single photo emitter. This is achieved by using CombiDisks having a flexible shaft. The flexible section allows for the bending of the CombiDisks so that the encoder disks are next to each other and tangent to the same vertical plane. This allows for the placement of both the x and the y sensors in a single plane. This will in turn allow for the two photo detectors to be integrated in a single semiconductor chip, saving a separate photo detector chip, and its associated packaging. This additional savings is significant since the packaging itself contributes to approximately one half of the cost of such a detector.
摘要翻译：一种用于通过单个光电检测器芯片和单个光电发射器替换两个单独的光电检测器芯片和两个光电发射器的方法和装置。这通过使用具有柔性轴的CombiDisk来实现。柔性部分允许CombiDisk的弯曲，使得编码器盘彼此相邻并且与相同的垂直平面相切。这允许将x和y传感器放置在单个平面中。这又将允许将两个光电检测器集成在单个半导体芯片中，从而节省单独的光电检测器芯片及其相关封装。这种额外的节省是重要的，因为包装本身有助于这种检测器的大约一半的成本。

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