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1. 发明申请

US20130181320A1 Manufacturing Techniques for Workpieces with Varying Topographies 有权
标题翻译：具有不同形貌的工件制造技术
公开(公告)号：US20130181320A1
公开(公告)日：2013-07-18
申请号：US13350010
申请日：2012-01-13
申请人： Chun-Chang Chen , Shih-Chi Fu , Wang-Pen Mo , Hung-Chang Hsieh
发明人： Chun-Chang Chen , Shih-Chi Fu , Wang-Pen Mo , Hung-Chang Hsieh
IPC分类号： H01L29/00 , B44C1/22 , H01L21/311
CPC分类号： H01L21/0276 , H01L21/32139 , H01L21/823431 , H01L21/823456
摘要： Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.
摘要翻译：一些实施例涉及用于处理工件的方法。在该方法中，在工件上方设有抗反射涂层。具有第一光致抗蚀剂色调的第一图案化光致抗蚀剂层设置在抗反射涂层上。在第一图案化光致抗蚀剂层上提供具有与第一光致抗蚀剂色调相反的第二光致抗蚀剂色调的第二图案化光致抗蚀剂层。开口延伸穿过第一和第二图案化的光致抗蚀剂层，以允许通过开口对工件施加处理。还公开了其他实施例。

2. 发明申请

US20130137266A1 MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES 有权
标题翻译：制造技术限制工件损坏与变化的地形
公开(公告)号：US20130137266A1
公开(公告)日：2013-05-30
申请号：US13306299
申请日：2011-11-29
申请人： Chun-Chang Chen , Shih-Chi Fu , Wang-Pen Mo , Hung Chang Hsieh
发明人： Chun-Chang Chen , Shih-Chi Fu , Wang-Pen Mo , Hung Chang Hsieh
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0271 , H01L27/11541 , H01L29/66795
摘要： Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.
摘要翻译：一些实施例涉及用于处理工件的方法。在该方法中，在工件上设置第一光致抗蚀剂层，其中第一光致抗蚀剂层具有第一光致抗蚀剂色调。图案化第一光致抗蚀剂层以提供暴露工件的第一部分的第一开口。然后在图案化的第一光刻胶层上提供第二光致抗蚀剂层，其中第二光致抗蚀剂层具有与第一光致抗蚀剂色调相反的第二光致抗蚀剂色调。然后对第二光致抗蚀剂层进行图案化以提供与第一开口至少部分重叠的第二开口，以限定重合的工件区域。然后对同时暴露的工件区域进行处理。还公开了其他实施例。

3. 发明授权

US08409456B2 Planarization method for high wafer topography 有权
标题翻译：高晶圆地形平面化方法
公开(公告)号：US08409456B2
公开(公告)日：2013-04-02
申请号：US13090763
申请日：2011-04-20
申请人： Shun-Wei Lan , Jieh-Jang Chen , Shih-Wei Lin , Feng-Jia Shiu , Hung Chang Hsieh
发明人： Shun-Wei Lan , Jieh-Jang Chen , Shih-Wei Lin , Feng-Jia Shiu , Hung Chang Hsieh
IPC分类号： B44C1/22
CPC分类号： H01L21/31058 , H01L21/31138
摘要： A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.
摘要翻译：一种用于平面化半导体器件的方法包括提供其中具有至少一个开口的衬底，每个开口限定下部和上部; 在所述基板上涂覆感光材料层，所述光敏材料层覆盖所述至少一个开口的下部和上部; 蚀刻光敏材料层以暴露至少一个开口的上部; 重复涂覆和蚀刻步骤以除去至少一个开口的上部下方的预定量; 在衬底上沉积绝缘层; 并且平坦化绝缘层，直到暴露至少一个开口的上部。

4. 发明申请

US20120270398A1 PLANARIZATION METHOD FOR HIGH WAFER TOPOGRAPHY 有权
标题翻译：高速地形平面化方法
公开(公告)号：US20120270398A1
公开(公告)日：2012-10-25
申请号：US13090763
申请日：2011-04-20
申请人： Shun-Wei LAN , Jieh-Jang CHEN , Shih-Wei LIN , Feng-Jia SHIU , Hung Chang HSIEH
发明人： Shun-Wei LAN , Jieh-Jang CHEN , Shih-Wei LIN , Feng-Jia SHIU , Hung Chang HSIEH
IPC分类号： H01L21/3105 , H01L21/306
CPC分类号： H01L21/31058 , H01L21/31138
摘要： A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.
摘要翻译：一种用于平面化半导体器件的方法包括提供其中具有至少一个开口的衬底，每个开口限定下部和上部; 在所述基板上涂覆感光材料层，所述光敏材料层覆盖所述至少一个开口的下部和上部; 蚀刻光敏材料层以暴露至少一个开口的上部; 重复涂覆和蚀刻步骤以除去至少一个开口的上部下方的预定量; 在衬底上沉积绝缘层; 并且平坦化绝缘层，直到暴露至少一个开口的上部。

5. 发明授权

US08236579B2 Methods and systems for lithography alignment 有权
标题翻译：光刻对准的方法和系统
公开(公告)号：US08236579B2
公开(公告)日：2012-08-07
申请号：US11686142
申请日：2007-03-14
申请人： Hsiao-Tzu Lu , Hung Chang Hsieh , Kuei Shun Chen , Hsueh-Hung Fu , Ching-Hua Hsieh , Shau-Lin Shue
发明人： Hsiao-Tzu Lu , Hung Chang Hsieh , Kuei Shun Chen , Hsueh-Hung Fu , Ching-Hua Hsieh , Shau-Lin Shue
IPC分类号： H01L21/00
CPC分类号： G03F7/70725 , G03F7/70358 , G03F7/70783 , H01L21/67288
摘要： Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.
摘要翻译：基于基板的曲率轮廓光刻曝光基板的方法和系统。

6. 发明授权

US07999910B2 System and method for manufacturing a mask for semiconductor processing 有权
标题翻译：用于制造半导体处理用掩模的系统和方法
公开(公告)号：US07999910B2
公开(公告)日：2011-08-16
申请号：US11115433
申请日：2005-04-27
申请人： Chia-Jen Chen , Hsin-Chang Lee , Sheng-Chi Chin , Hung Chang Hsieh , Burn Jeng Lin
发明人： Chia-Jen Chen , Hsin-Chang Lee , Sheng-Chi Chin , Hung Chang Hsieh , Burn Jeng Lin
IPC分类号： G03B27/32 , G03B27/58 , G03D5/00
CPC分类号： G03F7/38
摘要： The present disclosure provides a system and method for manufacturing a mask for semiconductor processing. In one example, the system includes at least one exposure unit configured to select a recipe for a later baking process in a post treatment unit, a buffer unit coupled to the exposure unit and configured to move the mask substrate from the exposure unit to the post treatment unit without exposing the mask substrate to the environment; and the post treatment unit coupled to the buffer unit and the exposure unit and configured to perform a baking process on the mask substrate using baking parameters associated with the recipe selected by the exposure unit.
摘要翻译：本公开提供了一种用于制造用于半导体处理的掩模的系统和方法。在一个示例中，系统包括至少一个曝光单元，其被配置为在后处理单元中选择用于稍后烘焙处理的配方，缓冲单元，其耦合到曝光单元并且被配置为将掩模基板从曝光单元移动到柱处理单元，而不将掩模基板暴露于环境中; 以及所述后处理单元，其耦合到所述缓冲单元和所述曝光单元，并且被配置为使用与由所述曝光单元选择的所述配方相关联的烘焙参数对所述掩模基板进行烘烤处理。

7. 发明授权

US07897297B2 Method and system for optimizing intra-field critical dimension uniformity using a sacrificial twin mask 有权
标题翻译：使用牺牲双掩模优化场内临界尺寸均匀性的方法和系统
公开(公告)号：US07897297B2
公开(公告)日：2011-03-01
申请号：US11763269
申请日：2007-06-14
申请人： Chih-Ming Ke , Tsai-Sheng Gau , Shinn-Sheng Yu , Hung-Chang Hsieh
发明人： Chih-Ming Ke , Tsai-Sheng Gau , Shinn-Sheng Yu , Hung-Chang Hsieh
IPC分类号： G03F1/00
CPC分类号： G03F1/44 , G03F1/00
摘要： Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.
摘要翻译：公开了一种用于优化集成电路的场内临界尺寸的方法和系统。提供了集成电路的第一掩模，其包括至少一个器件区域。通过复制第一掩模来提供第二掩模，并且使用第一和第二掩模将光刻操作提供给集成电路，其中使用第二掩模优化集成电路的临界尺寸。第二掩模包括多个牺牲图案，其可以是多个平坦图案或多个光栅图案。

8. 发明授权

US07697114B2 Method and apparatus for compensated illumination for advanced lithography 失效
标题翻译：用于高级光刻的补偿照明的方法和装置
公开(公告)号：US07697114B2
公开(公告)日：2010-04-13
申请号：US11424173
申请日：2006-06-14
申请人： Shih-Ming Chang , Wen-Chuan Wang , Chih-Cheng Chin , Chi-Lun Lu , Sheng-Chi Chin , Hung Chang Hsieh
发明人： Shih-Ming Chang , Wen-Chuan Wang , Chih-Cheng Chin , Chi-Lun Lu , Sheng-Chi Chin , Hung Chang Hsieh
IPC分类号： G03B27/54 , G03B27/72
CPC分类号： G03F7/701
摘要： Disclosed is a lithography system. The lithography system includes a source designed to provide energy; an imaging system configured to direct the energy onto a substrate to form a predefined image thereon, and defining an optical axis; and an aperture incorporated with the imaging system, the aperture having a plurality of transmitting regions defined along radial axis not parallel to the optical axis, and each transmitting region operable to transmit the energy with adjustable intensity.
摘要翻译：公开了一种光刻系统。光刻系统包括设计用于提供能量的源; 成像系统，被配置为将能量引导到衬底上以在其上形成预定图像，并且限定光轴; 以及与成像系统结合的孔，所述孔具有沿着不平行于光轴的径向轴线限定的多个透射区域，并且每个透射区域可操作以以可调节的强度透射能量。

9. 发明申请

US20070270003A1 POWER SUPPLY APPARATUS HAVING MULTIPLE POWER OUTPUT DEVICES 审中-公开
标题翻译：具有多个电力输出装置的电源装置
公开(公告)号：US20070270003A1
公开(公告)日：2007-11-22
申请号：US11534104
申请日：2006-09-21
申请人： Wen-Hsiang Lin , Szu-Lu Huang , Hung-Chang Hsieh
发明人： Wen-Hsiang Lin , Szu-Lu Huang , Hung-Chang Hsieh
IPC分类号： H01R13/648
CPC分类号： H01R13/6272 , H01R13/639
摘要： A power supply apparatus includes a main body, a power input device, a first power output device and a second power output device. The power input device is coupled to an input terminal of the main body. The first power output device includes a first cable and a first connector. The first cable is interconnected between a first output terminal of the main body and a first surface of the first connector. An extension part is extended from the first surface of the first connector. The second power output device includes a second cable and a second connector. A first surface of the second connector is suppressed by the extension part of the first connector to facilitate securely fixing the first connector and the second connector in a power socket, so that a regulated output voltage is outputted from the first and second output devices to the power socket.
摘要翻译：电源装置包括主体，电源输入装置，第一电力输出装置和第二电力输出装置。电源输入装置耦合到主体的输入端子。第一电力输出装置包括第一电缆和第一连接器。第一电缆在主体的第一输出端子和第一连接器的第一表面之间互连。延伸部分从第一连接器的第一表面延伸。第二电力输出装置包括第二电缆和第二连接器。第二连接器的第一表面被第一连接器的延伸部分抑制，以便将第一连接器和第二连接器牢固地固定在电源插座中，使得稳定的输出电压从第一和第二输出装置输出到电源插座。

10. 发明授权

US06312876B1 Method for placing identifying mark on semiconductor wafer 有权
标题翻译：在半导体晶片上放置识别标记的方法
公开(公告)号：US06312876B1
公开(公告)日：2001-11-06
申请号：US09349842
申请日：1999-07-08
申请人： Yung-Sheng Huang , Hung-Chang Hsieh
发明人： Yung-Sheng Huang , Hung-Chang Hsieh
IPC分类号： G03F726
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A tool and method for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.
摘要翻译：用于在半导体晶片上放置识别标记的工具和方法具有可以以表示识别字符的图案照亮的一束光纤。来自纤维的光在晶片制造期间聚焦在光致抗蚀剂层上，并且将点阵图案蚀刻到晶片中以表示字符。这些点太小，不能用人眼看到，但人物可以由人或机器读取。作为制造晶片的常规蚀刻步骤的一部分蚀刻该字符，并且由于一系列制造步骤遮蔽原始标记，因此容易重复该字符。

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