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1. 发明授权

US08431291B2 Intensity selective exposure photomask 有权
标题翻译：强度选择性曝光光掩模
公开(公告)号：US08431291B2
公开(公告)日：2013-04-30
申请号：US13281198
申请日：2011-10-25
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC分类号： G03F1/00 , G03F1/36
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
摘要翻译：还提供强度选择性曝光光掩模，还描述为渐变光掩模。光掩模包括包括第一子分解特征阵列的第一区域。第一个区域阻止了第一个入射辐射的百分比。光掩模还包括包括第二子分辨率特征阵列的第二区域。第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。

2. 发明申请

US20110289466A1 Table-Based DFM for Accurate Post-Layout Analysis 有权
标题翻译：基于表的DFM，用于精确的后期布局分析
公开(公告)号：US20110289466A1
公开(公告)日：2011-11-24
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

3. 发明授权

US08037575B2 Method for shape and timing equivalent dimension extraction 有权
标题翻译：形状和时间等值尺寸提取方法
公开(公告)号：US08037575B2
公开(公告)日：2011-10-18
申请号：US12211624
申请日：2008-09-16
申请人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
发明人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265 , Y10T16/2771
摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
摘要翻译：集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

4. 发明授权

US07954072B2 Model import for electronic design automation 有权
标题翻译：电子设计自动化模型导入
公开(公告)号：US07954072B2
公开(公告)日：2011-05-31
申请号：US11748604
申请日：2007-05-15
申请人： Ru-Gun Liu , Chih-Ming Lai , Wen-Chun Huang , Boren Luo , I-Chang Shin , Yao-Ching Ku , Cliff Hou
发明人： Ru-Gun Liu , Chih-Ming Lai , Wen-Chun Huang , Boren Luo , I-Chang Shin , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.
摘要翻译：公开了以安全格式提供处理参数的方法和系统。一方面，公开了一种向设计设备提供半导体制造处理参数的方法。该方法包括提供制造设施的一组处理参数; 从一组处理参数创建模型; 将模型转换为相应的一组内核; 将所述内核集合转换成相应的矩阵集合; 并将该组矩阵传送到设计设施。另一方面，公开了一种用于提供半导体制造处理参数的方法。该方法包括提供制造设施的一组处理参数; 从一组处理参数创建一个处理模型; 将处理模型加密成与多个EDA工具一起使用的格式; 并将加密的处理模型格式传送到设计设施。

5. 发明授权

US07685558B2 Method for detection and scoring of hot spots in a design layout 失效
标题翻译：设计布局中热点的检测和评分方法
公开(公告)号：US07685558B2
公开(公告)日：2010-03-23
申请号：US11682640
申请日：2007-03-06
申请人： Chih-Ming Lai , Ru-Gun Liu , I-Chang Shin , Yao-Ching Ku , Cliff Hou
发明人： Chih-Ming Lai , Ru-Gun Liu , I-Chang Shin , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to process image formation, and a third index sensitive to mask manufacturing error. The plurality of indices is then analyzed to identify at least one hotspot in the design layout. The at least one hotspot is then prioritized using an integrated hotspot scoring system. The integrated hotspot scoring system prioritizes hotspots based on a look-up table approach or an interpolation approach.
摘要翻译：提供了一种用于在设计布局中检测和评分热点的方法。针对设计布局中的多个位置导出多个索引。多个索引包括对设计布局的能量曝光敏感的第一索引，对过程图像形成敏感的第二索引以及对掩模制造误差敏感的第三索引。然后分析多个索引以识别设计布局中的至少一个热点。然后使用集成热点评分系统优先考虑至少一个热点。集成热点评分系统基于查找表方法或插值方法优先考虑热点。

6. 发明申请

US20090222785A1 METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION 有权
标题翻译：形状和时间等效尺寸提取方法
公开(公告)号：US20090222785A1
公开(公告)日：2009-09-03
申请号：US12211624
申请日：2008-09-16
申请人： Ying-Chou CHENG , Chih-Ming LAI , Ru-Gun LIU , Tsong-Hua OU , Min-Hong WU , Yih-Yuh DOONG , Hsiao-Shu CHAO , Yi-Kan CHENG , Yao-Ching KU , Cliff HOU
发明人： Ying-Chou CHENG , Chih-Ming LAI , Ru-Gun LIU , Tsong-Hua OU , Min-Hong WU , Yih-Yuh DOONG , Hsiao-Shu CHAO , Yi-Kan CHENG , Yao-Ching KU , Cliff HOU
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265 , Y10T16/2771
摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
摘要翻译：集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

7. 发明申请

US20070266362A1 Method for Detection and Scoring of Hot Spots in a Design Layout 失效
标题翻译：设计布局中热点检测和计分方法
公开(公告)号：US20070266362A1
公开(公告)日：2007-11-15
申请号：US11682640
申请日：2007-03-06
申请人： Chih-Ming Lai , Ru-Gun Liu , I-Chang Shin , Yao-Ching Ku , Cliff Hou
发明人： Chih-Ming Lai , Ru-Gun Liu , I-Chang Shin , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to process image formation, and a third index sensitive to mask manufacturing error. The plurality of indices is then analyzed to identify at least one hotspot in the design layout. The at least one hotspot is then prioritized using an integrated hotspot scoring system. The integrated hotspot scoring system prioritizes hotspots based on a look-up table approach or an interpolation approach.
摘要翻译：提供了一种用于在设计布局中检测和评分热点的方法。针对设计布局中的多个位置导出多个索引。多个索引包括对设计布局的能量曝光敏感的第一索引，对过程图像形成敏感的第二索引以及对掩模制造误差敏感的第三索引。然后分析多个索引以识别设计布局中的至少一个热点。然后使用集成热点评分系统优先考虑至少一个热点。集成热点评分系统基于查找表方法或插值方法优先考虑热点。

8. 发明申请

US20070265725A1 Model Import for Electronic Design Automation 有权
标题翻译：电子设计自动化模型导入
公开(公告)号：US20070265725A1
公开(公告)日：2007-11-15
申请号：US11748604
申请日：2007-05-15
申请人： Ru-Gun Liu , Chih-Ming Lai , Wen-Chun Huang , Boren Luo , I-Chang Shin , Yao-Ching Ku , Cliff Hou
发明人： Ru-Gun Liu , Chih-Ming Lai , Wen-Chun Huang , Boren Luo , I-Chang Shin , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F19/00
CPC分类号： G06F17/50
摘要： Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.
摘要翻译：公开了以安全格式提供处理参数的方法和系统。一方面，公开了一种向设计设备提供半导体制造处理参数的方法。该方法包括提供制造设施的一组处理参数; 从一组处理参数创建模型; 将模型转换为相应的一组内核; 将所述内核集合转换成相应的矩阵集合; 并将该组矩阵传送到设计设施。另一方面，公开了一种用于提供半导体制造处理参数的方法。该方法包括提供制造设施的一组处理参数; 从一组处理参数创建一个处理模型; 将处理模型加密成与多个EDA工具一起使用的格式; 并将加密的处理模型格式传送到设计设施。

9. 发明申请

US20060211254A1 Top patterned hardmask and method for patterning 有权
标题翻译：顶部图案化硬掩模和图案化方法
公开(公告)号：US20060211254A1
公开(公告)日：2006-09-21
申请号：US11084495
申请日：2005-03-18
申请人： George Liu , Vencent Chang , Norman Chen , Yao-Ching Ku , Chin-Hsiang Lin , Kuei Chen
发明人： George Liu , Vencent Chang , Norman Chen , Yao-Ching Ku , Chin-Hsiang Lin , Kuei Chen
IPC分类号： H01L21/467 , G03F1/00
CPC分类号： H01L21/31144 , G03F7/11 , H01L21/0274 , H01L21/0332 , H01L21/76807
摘要： A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.
摘要翻译：一种图案化硬掩模及其形成方法，所述方法包括提供包含对活化辐射敏感的上覆抗蚀剂的基底; 形成对激活辐射不敏感的上覆硬掩模; 将抗蚀剂通过硬掩模暴露于活化辐射; 烘烤抗蚀剂和硬掩模; 并开发硬掩模和抗蚀剂以形成图案化的抗蚀剂和图案化的硬掩模。

10. 发明授权

US06013397A Method for automatically forming a phase shifting mask 有权
标题翻译：自动形成相移掩模的方法
公开(公告)号：US06013397A
公开(公告)日：2000-01-11
申请号：US186127
申请日：1998-11-04
申请人： Chin-Lung Lin , Yao-Ching Ku
发明人： Chin-Lung Lin , Yao-Ching Ku
IPC分类号： G03F1/26 , G03F1/36 , G03F9/00
CPC分类号： G03F1/26 , G03F1/36
摘要： A method for automatically forming a sub-resolution PSM is provided. The shielding layer is designed by adding an assist feature to a peripheral region of an original shielding layer formed on a quartz substrate. Using an etching process with a etching mask, a portion of the original shielding layer is removed to form an original pattern and an assist feature. The assist feature is separated from the original pattern by a distance. A photoresist layer is tormed on the rim of the shielding layer so that the original pattern, half of the assist feature, and an exposed portion of the quartz substrate between the original pattern and the assist feature are exposed. A selective etching process is performed to etch the exposed portion of the quartz substrate to a certain depth so that it behaves like a phase shifting layer. After removing the photoresist layer, the sub-resolution PSM including the integrated circuit pattern and the assist feature is complete.
摘要翻译：提供了一种自动形成子分辨率PSM的方法。通过向形成在石英基板上的原始屏蔽层的外围区域添加辅助特征来设计屏蔽层。使用具有蚀刻掩模的蚀刻工艺，去除原始屏蔽层的一部分以形成原始图案和辅助特征。辅助功能与原始图案分开一段距离。光致抗蚀剂层被置于屏蔽层的边缘上，使原始图案（辅助特征的一半）和原始图案与辅助特征之间的石英基板的暴露部分露出。执行选择性蚀刻处理以将石英衬底的暴露部分蚀刻到一定深度，使得其表现为类似于移相层。在去除光致抗蚀剂层之后，包括集成电路图案和辅助特征的子分辨率PSM完成。

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