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1. 发明授权

US07167392B1 Non-volatile memory cell with improved programming technique 有权
标题翻译：具有改进编程技术的非易失性存储单元
公开(公告)号：US07167392B1
公开(公告)日：2007-01-23
申请号：US11183198
申请日：2005-07-15
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C11/34 , G11C14/00 , G11C16/04
CPC分类号： G11C14/00 , G11C7/06 , G11C16/0408
摘要： A non-volatile memory (NVM) cell splits its basic function, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell. The programming method for the cell utilizes a reverse Fowler-Nordheim tunneling mechanism with a very small programming current, allowing an entire NVM array to be programmed at one cycle.
摘要翻译：非易失性存储器（NVM）单元在四个PMOS晶体管结构中分离其基本功能，即编程，擦除，读取和控制，允许每个功能的独立优化。单元结构还包括嵌入式静态随机存取存储器（SRAM）单元，其利用锁存结构来预编程要写入单元的数据。该单元的编程方法利用具有非常小的编程电流的反向Fowler-Nordheim隧道机制，允许在一个周期对整个NVM阵列进行编程。

2. 发明授权

US07069461B1 Closed-loop, supply-adjusted RAM memory circuit 有权
标题翻译：闭环，电源调整RAM存储电路
公开(公告)号：US07069461B1
公开(公告)日：2006-06-27
申请号：US10351056
申请日：2003-01-24
申请人： Wai Cheong Chan , James Thomas Doyle , Pavel Poplevine , Murali Krishna Varadarajula , Hsing-Chien Roy Liu , Gordon Mortensen
发明人： Wai Cheong Chan , James Thomas Doyle , Pavel Poplevine , Murali Krishna Varadarajula , Hsing-Chien Roy Liu , Gordon Mortensen
IPC分类号： G06F1/04
CPC分类号： G11C5/14 , G11C7/1072 , G11C11/4074
摘要： The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.
摘要翻译：响应于时钟信号的频率的变化来调整存储器系统的电源电压。存储器系统测量从数据在存储器的输出到下一个时钟边沿的数据有效的时间，以确定时序值。当时钟频率从第一频率变化到第二频率时，定时值从第一值变为第二值。改变电源电压的大小，将定时值返回到第一个值。

3. 发明授权

US07042763B1 Programming method for nonvolatile memory cell 有权
标题翻译：非易失性存储单元的编程方法
公开(公告)号：US07042763B1
公开(公告)日：2006-05-09
申请号：US10895711
申请日：2004-07-08
申请人： Yuri Mirgorodski , Pavel Poplevine , Peter J. Hopper , Andrew J. Franklin
发明人： Yuri Mirgorodski , Pavel Poplevine , Peter J. Hopper , Andrew J. Franklin
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C2216/10
摘要： A method of selectively programming nonvolatile memory cells in which multiple programming voltages are used to obtain the desired voltage on the storage nodes of the cells selected for programming, while the storage nodes of unselected cells remain undisturbed.
摘要翻译：一种选择性地编程非易失性存储单元的方法，其中使用多个编程电压来获得所选择用于编程的单元的存储节点上的期望电压，而未选定单元的存储节点保持不受干扰。

4. 发明授权

US06420217B1 Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology 有权
标题翻译：用于在低电压技术中将集成熔丝元件编程为高电阻的装置的方法
公开(公告)号：US06420217B1
公开(公告)日：2002-07-16
申请号：US09632375
申请日：2000-08-03
申请人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
发明人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse. The transistor includes: a well region in a substrate, the well region forming the drain of the transistor; an insulating trench in the well; and a polysilicon gate extending over a portion of the substrate, a portion of the well and a portion of the trench, wherein upon reverse-biasing the junction between the well and the substrate a depletion region is formed which encompasses at least the entire portion of the surface region of the well over which the polysilicon extends.
摘要翻译：集成的熔丝元件能够被编程为低电压工艺技术中的高电阻。熔丝包括未掺杂的多晶硅层和硅化物层的堆叠。施加在堆叠上的电压增加直到发生第一附聚事件，由此在硅化物层中形成不连续性。电流进一步增加以引起第二聚集事件，从而增加不连续性的大小。每个附聚事件会增加保险丝的电阻。能够保持高电压的延伸漏极MOS晶体管与保险丝串联连接，以对熔丝进行编程。晶体管包括：衬底中的阱区，形成晶体管的漏极的阱区; 井中的绝缘沟槽; 以及在所述衬底的一部分上延伸的多晶硅栅极，所述阱的一部分和所述沟槽的一部分，其中在反向偏置所述阱和所述衬底之间的结点时，形成耗尽区，所述耗尽区至少包括多晶硅延伸的阱的表面区域。

5. 发明授权

US06218688B1 Schottky diode with reduced size 有权
标题翻译：肖特基二极管尺寸减小
公开(公告)号：US06218688B1
公开(公告)日：2001-04-17
申请号：US09280888
申请日：1999-03-29
申请人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
发明人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
IPC分类号： H01L27095
CPC分类号： H01L27/0811
摘要： The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.
摘要翻译：在本发明中，通过形成肖特基二极管通过场氧化物隔离区域，由常规肖特基二极管消耗的硅壳体减少。通过场氧化物隔离区域的蚀刻需要额外的蚀刻时间，其通过常规蚀刻步骤提供，其通常在接触形成期间指定50-100％的过蚀刻。

6. 发明授权

US6122204A Sense amplifier having a bias circuit with a reduced size 有权
标题翻译：具有减小尺寸的偏置电路的感测放大器
公开(公告)号：US6122204A
公开(公告)日：2000-09-19
申请号：US320413
申请日：1999-05-26
申请人： Pavel Poplevine , Alexander Kalnitsky , Albert Bergemont
发明人： Pavel Poplevine , Alexander Kalnitsky , Albert Bergemont
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/065
摘要： A sense amplifier places a low positive voltage, such as 0.1 to 0.3 volts, on a bit line instead of ground when a memory cell is read by utilizing a current source circuit to output a reference current that biases a Schottky diode. The current source circuit is implemented with a Schottky diode that utilizes the reverse-biased leakage current of the diode to form the reference current. The current source circuit can also be implemented with a current mirror circuit.
摘要翻译：当通过利用电流源电路读出存储单元以输出偏置肖特基二极管的参考电流时，读出放大器将位置线上的低正电压（例如0.1至0.3伏特）置于地线上而不是接地。电流源电路用肖特基二极管实现，其利用二极管的反向偏置漏电流形成参考电流。电流源电路也可以用电流镜电路来实现。

7. 发明授权

US6049202A Reference current generator with gated-diodes 有权
标题翻译：带门控二极管的参考电流发生器
公开(公告)号：US6049202A
公开(公告)日：2000-04-11
申请号：US191140
申请日：1998-11-13
申请人： Pavel Poplevine , Alexander Kalnitsky , Albert Bergemont
发明人： Pavel Poplevine , Alexander Kalnitsky , Albert Bergemont
IPC分类号： G05F3/24 , G05F3/16 , G05F3/02
CPC分类号： G05F3/245
摘要： A reference current generator outputs a reference current which is insensitive to temperature variations by utilizing two gated diodes to output currents. The currents output by the gated diodes are divided to produce the reference current which, due to the cancellation of terms, is defined by the ratio of the gate areas of the gated diodes. In addition, by utilizing two oscillators, which run at different frequencies, to drive the gated diodes, the reference current may alternately be defined by the ratio of the two frequencies.
摘要翻译：参考电流发生器通过利用两个门控二极管输出电流来输出对温度变化不敏感的参考电流。由门控二极管输出的电流被分压以产生参考电流，由于术语的消除，其由门控二极管的栅极面积的比定义。此外，通过利用以不同频率运行的两个振荡器来驱动门控二极管，参考电流可以交替地由两个频率的比率来定义。

8. 发明授权

US08363469B1 All-NMOS 4-transistor non-volatile memory cell 有权
标题翻译：全NMOS 4晶体管非易失性存储单元
公开(公告)号：US08363469B1
公开(公告)日：2013-01-29
申请号：US12698318
申请日：2010-02-02
申请人： Pavel Poplevine , Umer Khan , Hengyang (James) Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Umer Khan , Hengyang (James) Lin , Andrew J. Franklin
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/115
摘要： A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain. bulk, and gate electrodes of the programming, erase, and control transistors are then returned to the positive voltage, while setting the source, drain, and bulk electrodes of the read transistor to the inhibiting voltage.
摘要翻译：非易失性存储单元包括具有连接到存储节点的栅极的NMOS编程，读取，擦除和控制晶体管。擦除和控制晶体管具有互连的源极，漏极和体电极。通过将所有晶体管的源极，漏极，体积和栅极电极设置为正电压来对单元进行编程。在将编程晶体管的源极和漏极电极设置为正电压和编程晶体管的体电极至正电压或抑制电压的同时，将读取晶体管的源极，漏极和体电极施加抑制电压。然后，控制晶体管的源极，漏极和体电极斜坡到负的控制电压，同时将擦除晶体管的源极，漏极和体电极斜缓到负的擦除电压，然后返回到正的电压。来源，流失。然后将编程，擦除和控制晶体管的体积和栅电极返回到正电压，同时将读取晶体管的源极，漏极和体电极设置为抑制电压。

9. 发明授权

US08284600B1 5-transistor non-volatile memory cell 有权
标题翻译： 5晶体管非易失性存储单元
公开(公告)号：US08284600B1
公开(公告)日：2012-10-09
申请号：US12702061
申请日：2010-02-08
申请人： Pavel Poplevine , Ernes Ho , Umer Khan , Hengyang James Lin
发明人： Pavel Poplevine , Ernes Ho , Umer Khan , Hengyang James Lin
IPC分类号： G11C11/34
CPC分类号： G11C16/0441
摘要： A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.
摘要翻译：非易失性存储器（NVM）单元包括具有共同连接的源极，漏极和体区电极的NMOS控制晶体管和连接到存储节点的栅电极; 具有共连接的源极，漏极和体区电极的PMOS擦除晶体管和连接到存储节点的栅电极; 具有源极，漏极和体区电极的NMOS数据晶体管和连接到存储节点的栅极，所述体区电极连接到公共体节点; 所述第一NMOS栅极晶体管具有连接到所述NMOS数据晶体管的漏电极的源电极，漏电极，连接到所述公共体节点的体区电极和栅电极; 以及第二NMOS栅极晶体管，其具有连接到NMOS数据晶体管的源电极的漏电极，源电极，连接到公共体节点的体区电极和栅电极。

10. 发明申请

US20110242898A1 4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE 有权
标题翻译：具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元
公开(公告)号：US20110242898A1
公开(公告)日：2011-10-06
申请号：US12751012
申请日：2010-03-31
申请人： Pavel Poplevine , Ernes Ho , Hengyang James Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Hengyang James Lin , Andrew J. Franklin
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0441 , G11C16/10
摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
摘要翻译：非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。

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