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1. 发明授权

US08942053B2 Generating and amplifying differential signals 有权
标题翻译：生成和放大差分信号
公开(公告)号：US08942053B2
公开(公告)日：2015-01-27
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/02 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流镜电路。第一电流镜电路具有参考端和镜像端。第一电流镜电路的参考端耦合到第一节点，并且第一电流镜电路的镜像端耦合到第二节点。第二电流镜电路具有参考端和镜像端。第二电流镜电路的参考端耦合到第二节点，并且第二电流镜电路的镜像端耦合到第一节点。

2. 发明申请

US20130215693A1 TRACKING CAPACITIVE LOADS 有权
标题翻译：跟踪电容负载
公开(公告)号：US20130215693A1
公开(公告)日：2013-08-22
申请号：US13399877
申请日：2012-02-17
申请人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
发明人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要： A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译：确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。基于时间延迟，确定与时间延迟相对应的电容。使用具有确定的电容的电容器。电容器耦合到跟踪电路的跟踪单元的第一数据线。第一数据线的第一转变导致存储器单元的第二数据线的第一转变。

3. 发明授权

US08223571B2 Generating and amplifying differential signals 有权
标题翻译：生成和放大差分信号
公开(公告)号：US08223571B2
公开(公告)日：2012-07-17
申请号：US12839575
申请日：2010-07-20
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
摘要翻译：电路包括具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

4. 发明申请

US20100246311A1 CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL 有权
标题翻译：用于提供内部时钟信号的时钟发生器，存储器电路，系统和方法
公开(公告)号：US20100246311A1
公开(公告)日：2010-09-30
申请号：US12723077
申请日：2010-03-12
申请人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
发明人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C7/22 , G11C7/222 , G11C11/413
摘要： A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.
摘要翻译：时钟发生器包括第一输入端和第二输入端。第一输入端能够接收包括定义第一脉冲宽度的第一状态转变和第二状态转换的第一时钟信号。第二输入端能够接收具有第三状态转换的第二时钟信号。时间段从第一状态转换到第三状态转换。时钟发生器可以比较第一个脉冲宽度和时间周期。时钟发生器可以输出具有从第四状态转变到第五状态转变的第二脉冲宽度的第三时钟信号。根据第一脉冲宽度与时间段的比较，第三时钟信号的第五状态转换能够被第一时钟信号的第二状态转换或第二时钟信号的第三状态转换触发。

5. 发明授权

US07663959B2 Power up/down sequence scheme for memory devices 有权
标题翻译：存储器件的上电/下电序列方案
公开(公告)号：US07663959B2
公开(公告)日：2010-02-16
申请号：US12119092
申请日：2008-05-12
申请人： Derek Tao , Chungjz Lu , Annie-Li-Keow Lum
发明人： Derek Tao , Chungjz Lu , Annie-Li-Keow Lum
IPC分类号： G11C5/14
CPC分类号： G11C8/08
摘要： A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected.
摘要翻译：一种用于在断电过程期间控制存储器件的字线信号的方法，包括：将所述字线信号拉低至低逻辑状态; 在字线信号被下拉到低逻辑状态之后，将电流路径从外部电源断开到内部电源; 在从外部电源到内部电源的电流路径已经完全断开之后，将电流路径从外部接地电压断开到内部接地电压。

6. 发明授权

US07602641B2 Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure 有权
标题翻译：制造用于NVM单元结构的非易失性存储器（NVM）单元结构和程序偏置技术的方法
公开(公告)号：US07602641B2
公开(公告)日：2009-10-13
申请号：US12284890
申请日：2008-09-25
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
IPC分类号： G11C11/34 , G11C14/00
CPC分类号： G11C14/00
摘要： A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing conditions are applied to the NVM cell structure to implement program/operations.
摘要翻译：制造非易失性存储器（NVM）单元结构的方法包括形成包括第一和第二数据节点的第一NVM单元，第二NVM单元和SRAM单元。第一通道栅极结构连接在第一NVM单元和SRAM单元的第一数据节点之间，第一通道栅极结构响应于第一和第二状态的第一通道栅极信号以分别耦合和去耦合第一NVM单元，以及 SRAM单元。形成第一均衡结构以连接第一通道栅极结构和第一NVM单元，并且响应于第一均衡信号将第一NVM单元连接到地。第二通路栅极结构连接在第二NVM单元和SRAM单元的第二数据节点之间，第二通道栅极结构响应第二通路栅极信号的第一和第二状态，以分别耦合和去耦合第二NVM单元，以及 SRAM单元。第二均衡结构连接在第二通路栅极结构和第二NVM单元之间，第二均衡结构响应于第二均衡信号将第二NVM单元连接到地。将适当的偏置条件应用于NVM单元结构以实现程序/操作。

7. 发明申请

US20130088927A1 SYSTEM AND METHOD FOR GENERATING A CLOCK 有权
标题翻译：用于产生时钟的系统和方法
公开(公告)号：US20130088927A1
公开(公告)日：2013-04-11
申请号：US13253822
申请日：2011-10-05
申请人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
发明人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
IPC分类号： G11C8/18 , G11C7/10 , G11C7/00
CPC分类号： G11C7/222 , G11C11/412 , G11C11/413
摘要： A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro.
摘要翻译：存储器宏接收到第一个时钟。响应于第一时钟的第一时钟转换，产生第二时钟和第三时钟的第一转换。跟踪信号的跟踪转换是由第二个时钟引起的。基于第一时钟的第二时钟转换和跟踪信号的跟踪转变的稍后转换，产生第三时钟的第二转换。第三个时钟由内存宏的输入输出使用。

8. 发明申请

US20130010560A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20130010560A1
公开(公告)日：2013-01-10
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
发明人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
IPC分类号： H03F3/45 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。第一电流镜电路具有参考端和镜像端。第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。第二个当前次级电路具有参考端和镜像端。第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

9. 发明申请

US20090141579A1 Power Up/Down Sequence Scheme for Memory Devices 有权
标题翻译：内存设备的上电/下电顺序方案
公开(公告)号：US20090141579A1
公开(公告)日：2009-06-04
申请号：US12119092
申请日：2008-05-12
申请人： Derek Tao , Chungjz Lu , Annie-Li-Keow Lum
发明人： Derek Tao , Chungjz Lu , Annie-Li-Keow Lum
IPC分类号： G11C5/14
CPC分类号： G11C8/08
摘要： A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected.
摘要翻译：一种用于在断电过程期间控制存储器件的字线信号的方法，包括：将所述字线信号拉低至低逻辑状态; 在字线信号被下拉到低逻辑状态之后，将电流路径从外部电源断开到内部电源; 在从外部电源到内部电源的电流路径已经完全断开之后，将电流路径从外部接地电压断开到内部接地电压。

10. 发明授权

US07239558B1 Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle 有权
标题翻译：在单个周期中对非易失性存储器（NVM）单元阵列进行热电子注入编程的方法
公开(公告)号：US07239558B1
公开(公告)日：2007-07-03
申请号：US11235834
申请日：2005-09-26
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C11/34
CPC分类号： G11C11/005 , G11C14/00 , G11C16/0441
摘要： A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell and a plurality of cascoded NMOS pass gates. The cell structure reduces total programming time and provides the flexibility of programming the entire cell array simultaneously or one row or sector of the array at a time.
摘要翻译：非易失性存储器（NVM）单元在四个PMOS晶体管结构中分离其基本功能，即编程，擦除，读取和控制，允许每个单元功能的独立优化。单元结构还包括嵌入式静态随机存取存储器（SRAM）单元，其利用锁存结构来预编程要写入单元的数据和多个级联的NMOS通道门。单元结构减少总编程时间，并提供同时编程整个单元阵列或阵列的一行或多个扇区的灵活性。

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