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1. 发明授权

US06812069B2 Method for improving semiconductor process wafer CMP uniformity while avoiding fracture 失效
$Method for improving semiconductor process wafer CMP uniformity while avoiding fracture$
标题翻译：改善半导体工艺晶片CMP均匀性同时避免断裂的方法
公开(公告)号：US06812069B2
公开(公告)日：2004-11-02
申请号：US10322691
申请日：2002-12-17
申请人： Tung-Ching Tseng , Syun-Ming Jang , Chih-Hsiang Yao
发明人： Tung-Ching Tseng , Syun-Ming Jang , Chih-Hsiang Yao
IPC分类号： H01L2182
CPC分类号： H01L21/7684 , H01L21/3212 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.
摘要翻译：一种通过减少与虚拟特征相邻的应力集中来提高CMP抛光均匀性并减少或防止半导体晶片工艺表面中的裂纹的方法，包括提供半导体晶片工艺表面，其包括与活性特征相邻形成的活性特征和虚拟特征，以改善CMP抛光均匀性，所述虚拟特征各自被成形为在包括至少5个角部的所述半导体晶片工艺表面中限定封闭区域; 以及在所述半导体晶片处理表面上执行CMP处理。

2. 发明授权

US06794226B2 Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication 有权
$Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication$
标题翻译：掺入由难熔金属硅 - 氮形成的元件的半导体器件及其制造方法
公开(公告)号：US06794226B2
公开(公告)日：2004-09-21
申请号：US10374395
申请日：2003-02-26
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2182
CPC分类号： H01L21/76849 , H01L21/7687 , H01L21/76888 , H01L23/5258 , H01L27/0629 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.
摘要翻译：公开了一种半导体结构，其包括由难熔金属 - 硅 - 氮形成的熔丝，扩散阻挡层或电容器的至少一个电路元件。还公开了一种通过难熔金属硅 - 氮材料制造这种半导体结构的方法，其包括熔丝元件，扩散阻挡层，电阻器或电容器。要使用的合适的难熔金属 - 硅 - 氮材料是TaSiN，其通过改变Ta:Si:N的比例来提供宽范围的电阻率。本发明提供了通过TaSiN层的单个沉积工艺可以形成扩散阻挡层，保险丝，电容器和电阻器的各种组件的优点，然后通过热处理或离子注入对各种组分进行选择性掩蔽和处理，选择性地改变其电阻率，同时保持其他屏蔽元件具有相同的电阻率。

3. 发明授权

US06773967B1 Method to prevent antifuse Si damage using sidewall spacers 有权
标题翻译：使用侧壁间隔物防止反熔丝Si损伤的方法
公开(公告)号：US06773967B1
公开(公告)日：2004-08-10
申请号：US10037586
申请日：2002-01-04
申请人： Hsueh-Heng Liu
发明人： Hsueh-Heng Liu
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an antifuse interconnect structure, for a one-time fusible link, with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the sidewalls of the amorphous silicon layer protected by critical silicon nitride sidewall spacers, during the patterning/etch procedure of the overlying metal layer. The protective sidewall spacers prevent the amorphous Si antifuse from being etched by subsequent processes.
摘要翻译：已经开发了用于形成具有现场可编程门阵列的一次性可熔链路的反熔丝互连结构的方法。该工艺的特征在于在上覆金属层的图案化/蚀刻过程期间使用用作反熔丝层的非晶硅层，非晶硅层的侧壁由临界氮化硅侧壁间隔物保护。保护性侧壁间隔物防止非晶Si反熔丝被后续工艺蚀刻。

4. 发明授权

US06730547B2 Integrated circuit device and fabrication using metal-doped chalcogenide materials 有权
标题翻译：集成电路器件和使用金属掺杂的硫族化物材料的制造
公开(公告)号：US06730547B2
公开(公告)日：2004-05-04
申请号：US10285462
申请日：2002-11-01
申请人： Jiutao Li , Allen McTeer
发明人： Jiutao Li , Allen McTeer
IPC分类号： H01L2182
CPC分类号： C23C14/5846 , C23C14/0623 , C23C14/544 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/1658
摘要： Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.
摘要翻译：形成掺杂金属的硫族化物层的方法和包含这种掺杂的硫族化物层的器件包括使用等离子体来诱导金属与金属沉积同时扩散到硫族化物层中。等离子体包含至少一种低原子量的惰性气体，例如氖或氦。等离子体具有足以溅射金属靶的溅射产率和其发射光谱的UV分量足以引起溅射金属扩散到硫族化物层中。使用这种方法，可以在原位在掺杂的硫族化物层上形成导电层。在诸如非挥发性硫族化物存储器件的集成电路器件中，与金属沉积同时掺杂硫族化物层并且通过掺杂硫族化物层而原位形成导电层减少了由于移动器件衬底而引起的污染问题和物理损坏从工具到工具，从而有助于提高设备的可靠性。

5. 发明授权

US06649452B2 Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer 有权
标题翻译：用于制造用于将集成电路设计转移到半导体晶片的光刻掩模版的方法
公开(公告)号：US06649452B2
公开(公告)日：2003-11-18
申请号：US10085960
申请日：2002-02-28
申请人： Kevin D. Lucas , William L. Wilkinson , Cesar Garza
发明人： Kevin D. Lucas , William L. Wilkinson , Cesar Garza
IPC分类号： H01L2182
CPC分类号： G03F1/78 , G03F1/36
摘要： A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.
摘要翻译：在设计图案中具有亚分辨特征的光刻掩模版用于控制半导体制造工艺中的关键尺寸。在确定设计和处理特征的位置之后，在不具有设计和处理特征的区域中形成分解特征。分解特征可以基本上填满没有设计处理特征的所有区域，或者相反地，选择性地填充该区域的部分。在一个实施例中，没有设计和处理特征的区域的宽度小于特征宽度的两倍。分解特征的存在导致对半导体处理中的特征的小尺寸的改进的控制，从而增加产量和装置性能。

6. 发明授权

US06649451B1 Structure and method for wafer comprising dielectric and semiconductor 失效
标题翻译：包括电介质和半导体的晶片的结构和方法
公开(公告)号：US06649451B1
公开(公告)日：2003-11-18
申请号：US09776000
申请日：2001-02-02
申请人： Michael A. Vyvoda , James M. Cleeves , Calvin K. Li , Samuel V. Dunton
发明人： Michael A. Vyvoda , James M. Cleeves , Calvin K. Li , Samuel V. Dunton
IPC分类号： H01L2182
CPC分类号： H01L21/76224 , H01L21/76819 , H01L23/5254 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： Wafers of the present invention comprise a semiconductor layer and a dielectric layer. The semiconductor layer is patterned to form semiconductor regions, and the dielectric layer is deposited on top of the semiconductor layer. Chemical mechanical planarization (CMP) is performed to remove a portion of the dielectric layer, exposing the upper surfaces of the semiconductor regions. The amount of CMP necessary to expose all of the semiconductor regions on the wafer is reduced, because the dielectric is targeted to deposit up to the upper edge of the semiconductor regions in the spaces in between the semiconductor regions. This technique reduces non-uniformities in the thickness of the dielectric and semiconductor layers across the wafer. The thickness of the dielectric or semiconductor layer deposited on polish monitor pads located at the edges of each die may be monitored to determine when enough CMP has been performed to expose each of the semiconductor regions.
摘要翻译：本发明的晶片包括半导体层和电介质层。图案化半导体层以形成半导体区域，并且电介质层沉积在半导体层的顶部上。执行化学机械平面化（CMP）以去除电介质层的一部分，暴露半导体区域的上表面。由于电介质被靶向沉积到半导体区域之间的空间中的半导体区域的上边缘，因此减小了使晶片上的所有半导体区域露出所需的CMP量。该技术降低了跨晶片的电介质层和半导体层的厚度的不均匀性。可以监测沉积在位于每个管芯边缘的抛光监测器焊盘上的电介质层或半导体层的厚度，以确定何时已经执行了足够的CMP来暴露每个半导体区域。

7. 发明授权

US06613612B2 Fuse in semiconductor device and fabricating method thereof 失效
公开(公告)号：US06613612B2
公开(公告)日：2003-09-02
申请号：US10201928
申请日：2002-07-25
申请人： Hyun-Suck Park
发明人： Hyun-Suck Park
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a semiconductor substrate, an insulating layer on the semiconductor substrate wherein a groove is patterned to a predetermined depth in an upper surface of the insulating layer, a fuse layer at sidewalls and on a bottom of the groove, and a wire connected electrically to the fuse layer.

8. 发明授权

US06607944B1 Method of making memory cell arrays 有权
标题翻译：制造存储单元阵列的方法
公开(公告)号：US06607944B1
公开(公告)日：2003-08-19
申请号：US09918345
申请日：2001-07-30
申请人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
发明人： Luan Tran , D. Mark Duncan , Tyler A. Lowrey , Rob B. Kerr , Kris K. Brown
IPC分类号： H01L2182
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10885
摘要： A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.
摘要翻译：存储器件包括存储器单元，位线，通常与位线平行地运行的有源区线以及在每个有源区域线中形成的晶体管，并将存储单元电耦合到相应的位线。每个位线包括以一角度与有源区域线的相应部分相交的倾斜部分。将位线电耦合到有源区域线的部分的触点形成在通常由位线到有源区域线的成角度的交叉点限定的区域中。存储器单元可以具有约6F2的面积，并且位线可以以折叠位线配置耦合到读出放大器。每个位线包括第一电平部分和第二电平部分。

9. 发明授权

US06551864B2 Fuse for use in a semiconductor device, and semiconductor devices including the fuse 有权
公开(公告)号：US06551864B2
公开(公告)日：2003-04-22
申请号：US10073758
申请日：2002-02-11
申请人： Kenneth W. Marr , Michael P. Violette
发明人： Kenneth W. Marr , Michael P. Violette
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

10. 发明授权

US06541312B2 Formation of antifuse structure in a three dimensional memory 有权
标题翻译：在三维记忆体中形成反熔丝结构
公开(公告)号：US06541312B2
公开(公告)日：2003-04-01
申请号：US09746083
申请日：2000-12-22
申请人： James M. Cleeves , Michael A. Vyvoda , N. Johan Knall
发明人： James M. Cleeves , Michael A. Vyvoda , N. Johan Knall
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material. In the second embodiment of the present invention the array comprises a first plurality of spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric is recessed below the top surface of the semiconductor material. An antifuse material is formed on the top semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor film is formed on the antifuse material.
摘要翻译：本发明涉及新颖的反熔丝阵列及其制造方法。根据本发明的实施例，阵列包括具有顶部半导体材料的多个第一间隔开的轨道堆叠。填充电介质位于第一多个间隔开的轨道堆叠之间，其中填充电介质延伸到半导体材料的顶表面之上。在第一多个间隔开的轨道堆叠的半导体材料的顶部上形成反熔丝材料。在反熔丝材料上形成具有下半导体材料的第二多个间隔开的轨道堆叠。在本发明的第二实施例中，阵列包括具有顶部半导体材料的第一多个间隔开的轨道堆叠。填充电介质位于第一多个间隔开的轨道堆叠之间，其中填充电介质凹陷在半导体材料的顶表面下方。在第一多个间隔开的轨道堆叠的顶部半导体材料上形成反熔丝材料。在反熔丝材料上形成具有下半导体膜的第二多个间隔开的轨道堆叠。

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