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1. 发明授权

US08284600B1 5-transistor non-volatile memory cell 有权
标题翻译： 5晶体管非易失性存储单元
公开(公告)号：US08284600B1
公开(公告)日：2012-10-09
申请号：US12702061
申请日：2010-02-08
申请人： Pavel Poplevine , Ernes Ho , Umer Khan , Hengyang James Lin
发明人： Pavel Poplevine , Ernes Ho , Umer Khan , Hengyang James Lin
IPC分类号： G11C11/34
CPC分类号： G11C16/0441
摘要： A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node; an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node; the first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode, a bulk region electrode connected to the common bulk node, and a gate electrode; and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode, a bulk region electrode connected to the common bulk node, and a gate electrode.
摘要翻译：非易失性存储器（NVM）单元包括具有共同连接的源极，漏极和体区电极的NMOS控制晶体管和连接到存储节点的栅电极; 具有共连接的源极，漏极和体区电极的PMOS擦除晶体管和连接到存储节点的栅电极; 具有源极，漏极和体区电极的NMOS数据晶体管和连接到存储节点的栅极，所述体区电极连接到公共体节点; 所述第一NMOS栅极晶体管具有连接到所述NMOS数据晶体管的漏电极的源电极，漏电极，连接到所述公共体节点的体区电极和栅电极; 以及第二NMOS栅极晶体管，其具有连接到NMOS数据晶体管的源电极的漏电极，源电极，连接到公共体节点的体区电极和栅电极。

2. 发明申请

US20110242898A1 4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE 有权
标题翻译：具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元
公开(公告)号：US20110242898A1
公开(公告)日：2011-10-06
申请号：US12751012
申请日：2010-03-31
申请人： Pavel Poplevine , Ernes Ho , Hengyang James Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Hengyang James Lin , Andrew J. Franklin
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0441 , G11C16/10
摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
摘要翻译：非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。

3. 发明授权

US08159877B2 Method of directly reading output voltage to determine data stored in a non-volatile memory cell 有权
标题翻译：直接读取输出电压以确定存储在非易失性存储单元中的数据的方法
公开(公告)号：US08159877B2
公开(公告)日：2012-04-17
申请号：US12731589
申请日：2010-03-25
申请人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0441 , G11C16/06
摘要： An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling.
摘要翻译： NVM单元设计使得能够直接读取单元输出电压以确定存储在单元中的数据，同时提供低电流消耗和采用反向Fowler-Nordheim隧道的简单程序序列。

4. 发明授权

US08213227B2 4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure 有权
标题翻译：具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元
公开(公告)号：US08213227B2
公开(公告)日：2012-07-03
申请号：US12751012
申请日：2010-03-31
申请人： Pavel Poplevine , Ernes Ho , Hengyang (James) Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Hengyang (James) Lin , Andrew J. Franklin
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0441 , G11C16/10
摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
摘要翻译：非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。

5. 发明申请

US20120014183A1 3 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB 审中-公开
标题翻译： 3晶体管（N / P / N）不具有程序干扰的非易失性存储单元
公开(公告)号：US20120014183A1
公开(公告)日：2012-01-19
申请号：US12837835
申请日：2010-07-16
申请人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
摘要翻译：非易失性存储器（NVM）单元结构包括NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS数据晶体管和连接到数据存储节点的栅电极。

6. 发明申请

US20110235425A1 METHOD OF DIRECTLY READING OUTPUT VOLTAGE TO DETERMINE DATA STORED IN A NON-VOLATILE MEMORY CELL 有权
标题翻译：直接读取输出电压以确定存储在非易失性存储器单元中的数据的方法
公开(公告)号：US20110235425A1
公开(公告)日：2011-09-29
申请号：US12731589
申请日：2010-03-25
申请人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Umer Khan , Andrew J. Franklin
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C16/06
摘要： An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling.
摘要翻译： NVM单元设计使得能够直接读取单元输出电压以确定存储在单元中的数据，同时提供低电流消耗和采用反向Fowler-Nordheim隧道的简单程序序列。

7. 发明授权

US06642587B1 High density ROM architecture 有权
标题翻译：高密度ROM架构
公开(公告)号：US06642587B1
公开(公告)日：2003-11-04
申请号：US10214021
申请日：2002-08-07
申请人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin , Ernes Ho
发明人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin , Ernes Ho
IPC分类号： H01L2976
CPC分类号： H01L27/11246 , G11C17/123 , H01L27/112
摘要： A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.
摘要翻译：提供减小尺寸和功耗的ROM阵列。 ROM的位单元提供了当晶体管设置在位线和字线之间时，第一类型的信息被存储在位单元中，并且第二类型的信息被存储在单元中，当没有晶体管设置在单元之间时位线和字线。在晶体管形成在位线和字线之间的情况下，在位单元中提供位线和可以在衬底中形成晶体管漏极的区域之间的接触。在位单元在字线和位线之间不提供晶体管的情况下，在位线和可以形成晶体管漏极的区域之间不提供接触。此外，在位单元不在位线和字线之间提供晶体管的情况下，衬底中的位单元区域可以基本上由隔离电介质材料组成。

8. 发明授权

US07453726B1 Non-volatile memory cell with improved programming technique and density 有权
标题翻译：具有改进的编程技术和密度的非易失性存储单元
公开(公告)号：US07453726B1
公开(公告)日：2008-11-18
申请号：US11656609
申请日：2007-01-23
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
IPC分类号： G11C11/34 , G11C14/00
CPC分类号： G11C14/00
摘要： A single 4-transistor non-volatile memory (NVM) cell includes a shared static random access memory cell. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the shared SRAM cell structure, allows an entire cell array to be programmed at two cycles. A single NVM cell approach with shared SRAM allows a 50% area reduction with an insignificant increase in program time.
摘要翻译：单个4晶体管非易失性存储器（NVM）单元包括共享静态随机存取存储单元。 NVM单元利用反向Fowler-Nordheim隧道编程技术，其结合共享的SRAM单元结构，允许在两个周期对整个单元阵列进行编程。具有共享SRAM的单个NVM单元方案允许减少50％的面积，并且程序时间不会显着增加。

9. 发明授权

US07602641B2 Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure 有权
标题翻译：制造用于NVM单元结构的非易失性存储器（NVM）单元结构和程序偏置技术的方法
公开(公告)号：US07602641B2
公开(公告)日：2009-10-13
申请号：US12284890
申请日：2008-09-25
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
IPC分类号： G11C11/34 , G11C14/00
CPC分类号： G11C14/00
摘要： A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing conditions are applied to the NVM cell structure to implement program/operations.
摘要翻译：制造非易失性存储器（NVM）单元结构的方法包括形成包括第一和第二数据节点的第一NVM单元，第二NVM单元和SRAM单元。第一通道栅极结构连接在第一NVM单元和SRAM单元的第一数据节点之间，第一通道栅极结构响应于第一和第二状态的第一通道栅极信号以分别耦合和去耦合第一NVM单元，以及 SRAM单元。形成第一均衡结构以连接第一通道栅极结构和第一NVM单元，并且响应于第一均衡信号将第一NVM单元连接到地。第二通路栅极结构连接在第二NVM单元和SRAM单元的第二数据节点之间，第二通道栅极结构响应第二通路栅极信号的第一和第二状态，以分别耦合和去耦合第二NVM单元，以及 SRAM单元。第二均衡结构连接在第二通路栅极结构和第二NVM单元之间，第二均衡结构响应于第二均衡信号将第二NVM单元连接到地。将适当的偏置条件应用于NVM单元结构以实现程序/操作。

10. 发明申请

US20090129162A1 Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure 有权
标题翻译：制造用于NVM单元结构的非易失性存储器（NVM）单元结构和程序偏置技术的方法
公开(公告)号：US20090129162A1
公开(公告)日：2009-05-21
申请号：US12284890
申请日：2008-09-25
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Andrew Cao , Ernes Ho
IPC分类号： G11C16/04 , G11C16/06 , H01L21/336
CPC分类号： G11C14/00
摘要： A method of making a non-volatile memory (NVM) cell structure comprises the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing conditions are applied to the NVM cell structure to implement program/operations.
摘要翻译：制造非易失性存储器（NVM）单元结构的方法包括形成包括第一和第二数据节点的第一NVM单元，第二NVM单元和SRAM单元。第一通道栅极结构连接在第一NVM单元和SRAM单元的第一数据节点之间，第一通道栅极结构响应于第一和第二状态的第一通道栅极信号以分别耦合和去耦合第一NVM单元，以及 SRAM单元。形成第一均衡结构以连接第一通道栅极结构和第一NVM单元，并且响应于第一均衡信号将第一NVM单元连接到地。第二通路栅极结构连接在第二NVM单元和SRAM单元的第二数据节点之间，第二通道栅极结构响应第二通路栅极信号的第一和第二状态，以分别耦合和去耦合第二NVM单元，以及 SRAM单元。第二均衡结构连接在第二通路栅极结构和第二NVM单元之间，第二均衡结构响应于第二均衡信号将第二NVM单元连接到地。将适当的偏置条件应用于NVM单元结构以实现程序/操作。

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