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1. 发明申请

US20140063958A1 N-Channel Multi-Time Programmable Memory Devices 有权
标题翻译： N通道多时间可编程存储器件
公开(公告)号：US20140063958A1
公开(公告)日：2014-03-06
申请号：US13600792
申请日：2012-08-31
申请人： Yi He , Xiang Lu , Albert Bergemont
发明人： Yi He , Xiang Lu , Albert Bergemont
IPC分类号： G11C16/10
CPC分类号： G11C16/0408 , G11C2216/10
摘要： N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.
摘要翻译：具有N-导电类型衬底，N导电类型衬底中的第一和第二P导电类型阱的N沟道多时间可编程存储器件，形成在第一P导电型阱中的N导电型源极和漏极区源极和漏极区域被沟道区域分隔，N导电型衬底上的氧化物层; 以及在N导电类型衬底中在沟道区域上延伸超过第二P导电类型的浮栅，多时间可编程存储单元可通过热电子注入进行编程，并可通过热空穴注入进行擦除。

2. 发明授权

US08405115B2 Light sensor using wafer-level packaging 有权
标题翻译：光传感器采用晶圆级封装
公开(公告)号：US08405115B2
公开(公告)日：2013-03-26
申请号：US12361426
申请日：2009-01-28
申请人： Arkadii V. Samoilov , Albert Bergemont , Chiung-C. Lo , Prashanth Holenarsipur , James Patrick Long
发明人： Arkadii V. Samoilov , Albert Bergemont , Chiung-C. Lo , Prashanth Holenarsipur , James Patrick Long
IPC分类号： H01L33/00
CPC分类号： H01L31/18 , H01L27/144 , H01L31/101 , H01L2224/05001 , H01L2224/05008 , H01L2224/051 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/13 , H01L2924/00014
摘要： The present invention provides systems, devices and methods for fabricating miniature low-power light sensors. With the present invention, a light sensitive component, such as a diode, is fabricated on the front side of a silicon wafer. Connectivity from the front side of the wafer to the back side of the wafer is provided by a through silicon via. Solder bumps are then placed on the back side of the wafer to provide coupling to a printed circuit board. The techniques described in the present invention may also be applied to other types of semiconductor devices, such as light-emitting diodes, image sensors, pressure sensors, and flow sensors.
摘要翻译：本发明提供用于制造微型低功率光传感器的系统，装置和方法。利用本发明，在硅晶片的正面上制造诸如二极管的光敏元件。从晶片的前侧到晶片的背面的连接通过硅通孔提供。然后将焊料凸块放置在晶片的背面，以提供与印刷电路板的耦合。本发明中描述的技术也可以应用于其他类型的半导体器件，例如发光二极管，图像传感器，压力传感器和流量传感器。

3. 发明申请

US20080186773A1 One or multiple-times programmable device 有权
标题翻译：一个或多个可编程器件
公开(公告)号：US20080186773A1
公开(公告)日：2008-08-07
申请号：US11703922
申请日：2007-02-06
申请人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar
发明人： Albert Bergemont , David Kuan-Yu Liu , Venkatraman Prabhakar
IPC分类号： G11C16/06 , H01L21/336 , H01L29/788
CPC分类号： H01L29/7885 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.
摘要翻译：用于一次或多次可编程存储器件的方法和装置，包括计算机程序产品。半导体可以包括衬底的有源区，衬底上的薄氧化层，第一和第二多晶硅层以及第一和第二金属层。第一多晶硅层可以具有浮置栅极，有源区可以基本上垂直于浮置栅极，并且第二多晶硅层可以包括控制栅极。第一金属层可以包括连接到第一n扩散区域的位线，其中位线基本上垂直于浮动栅极。第二金属层可以包括字线和源极线。字线可以连接到控制栅极，并且源极线可以连接到第二n扩散区域。薄栅氧化物可以具有65和75埃之间的厚度。

4. 发明授权

US06606265B2 Common source EEPROM and flash memory 有权
公开(公告)号：US06606265B2
公开(公告)日：2003-08-12
申请号：US10002607
申请日：2001-10-30
申请人： Albert Bergemont , Gregorio Spadea
发明人： Albert Bergemont , Gregorio Spadea
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0425
摘要： A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

5. 发明授权

US06482723B1 Method for forming self-aligned floating gates 有权
标题翻译：用于形成自对准浮动栅极的方法
公开(公告)号：US06482723B1
公开(公告)日：2002-11-19
申请号：US09666810
申请日：2000-09-21
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L2104
CPC分类号： H01L27/11521 , H01L27/115
摘要： Self-aligned floating gates are formed to have precisely defined lengths and positions. The floating gates are formed by first forming a number of shallow trench isolation regions that have substantially planar top surfaces that lie above the top surface of the semiconductor material. A layer of dielectric is formed on the semiconductor material, followed by the formation of a first layer of polysilicon. The first layer of polysilicon is then planarized so that the first layer of polysilicon is removed from the isolation regions. In subsequent steps, the polysilicon is again etched to form the floating gates. As a result of the planarization, the lengths of the floating gates are defined by the spacing between isolation regions, and the positions of the floating gates are precisely defined.
摘要翻译：自对准浮动栅极形成为具有精确限定的长度和位置。浮动栅极通过首先形成许多浅沟槽隔离区域形成，该区域具有位于半导体材料的顶表面之上的基本平坦的顶表面。在半导体材料上形成电介质层，随后形成第一层多晶硅。然后将第一层多晶硅平坦化，使得第一层多晶硅从隔离区域移除。在随后的步骤中，再次蚀刻多晶硅以形成浮栅。作为平坦化的结果，浮动栅极的长度由隔离区域之间的间隔限定，并且浮动栅极的位置被精确地限定。

6. 发明授权

US06414872B1 Compact non-volatile memory device and memory array 有权
标题翻译：紧凑型非易失性存储器件和存储器阵列
公开(公告)号：US06414872B1
公开(公告)日：2002-07-02
申请号：US09598929
申请日：2000-06-21
申请人： Albert Bergemont , Pascale Francis
发明人： Albert Bergemont , Pascale Francis
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0433 , G11C2216/10
摘要： A compact non-volatile memory device and memory array that are compatible with conventional MOS device processing. The compact non-volatile memory device includes a PMOS storage transistor with a floating gate in series with a PMOS access transistor. Since both of these PMOS transistors can be disposed in a single N-type well region, the size of the compact non-volatile memory device is relatively small. Another MOS processing compatible compact non-volatile memory device is formed in a semiconductor substrate of a first conductivity type (typically P-type) that includes a well region of a second conductivity type (typically N-type). Such a device also includes first source and drain regions of the first conductivity type, a first channel region defined therebetween, and a floating gate. This device also includes second source and drain regions of the first conductivity type, a second channel region defined therebetween, and a gate. The first and second source and drain regions and first and second channel regions are formed in the well region. The compact non-volatile memory array includes a plurality of traversing bit and word lines and a plurality of the compact non-volatile memory devices. Each compact non-volatile memory device includes a PMOS storage transistor with a floating gate and a serially connected PMOS access transistor. In addition, each compact non-volatile memory device is electrically connected to a bit line via the PMOS storage transistor's source and electrically connected to a word lines via the PMOS access transistor's gate.
摘要翻译：与常规MOS器件处理兼容的紧凑型非易失性存储器件和存储器阵列。紧凑型非易失性存储器件包括具有与PMOS存取晶体管串联的浮动栅极的PMOS存储晶体管。由于这两个PMOS晶体管都可以设置在单个N型阱区域中，所以小型非易失性存储器件的尺寸相对较小。另一种MOS处理兼容的紧凑型非易失性存储器件形成在包括第二导电类型（通常为N型）的阱区的第一导电类型（通常为P型）的半导体衬底中。这种器件还包括第一导电类型的第一源极和漏极区域，其间限定的第一沟道区域和浮置栅极。该器件还包括第一导电类型的第二源极和漏极区域，在其间限定的第二沟道区域和栅极。第一和第二源极和漏极区域以及第一和第二沟道区域形成在阱区域中。紧凑型非易失性存储器阵列包括多个遍历位和字线以及多个紧凑型非易失性存储器件。每个紧凑型非易失性存储器件包括具有浮置栅极和串联连接的PMOS存取晶体管的PMOS存储晶体管。此外，每个紧凑型非易失性存储器件经由PMOS存储晶体管的源极电连接到位线，并且经由PMOS存取晶体管的栅极电连接到字线。

7. 发明授权

US06380054B1 Schottky diode with reduced size 有权
标题翻译：肖特基二极管尺寸减小
公开(公告)号：US06380054B1
公开(公告)日：2002-04-30
申请号：US09717591
申请日：2000-11-21
申请人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
发明人： Alexander Kalnitsky , Pavel Poplevine , Albert Bergemont
IPC分类号： H01L2128
CPC分类号： H01L27/0811
摘要： The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.
摘要翻译：在本发明中，通过形成肖特基二极管通过场氧化物隔离区域，由常规肖特基二极管消耗的硅壳体减少。通过场氧化物隔离区域的蚀刻需要额外的蚀刻时间，其通过常规蚀刻步骤提供，其通常在接触形成期间指定50-100％的过蚀刻。

8. 发明授权

US06362050B1 Method for forming a non-volatile memory cell that eliminates substrate trenching 有权
公开(公告)号：US06362050B1
公开(公告)日：2002-03-26
申请号：US09732381
申请日：2000-12-07
申请人： Alexander Kalnitsky , Albert Bergemont
发明人： Alexander Kalnitsky , Albert Bergemont
IPC分类号： H01L21336
摘要： In a non-volatile memory cell that has a select transistor and a memory transistor, the substrate trenching that occurs when the gate of the select transistor and the stacked gate of the memory transistor are initially defined is eliminated by forming the gate of the select transistor and the stacked gate of the memory transistor to have substantially the same step height.

9. 发明授权

US06249010B1 Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture 有权
标题翻译：具有多晶硅接触插头的介质型反熔丝电池及其制造方法
公开(公告)号：US06249010B1
公开(公告)日：2001-06-19
申请号：US09135536
申请日：1998-08-17
申请人： Albert Bergemont , Alexander Kalnitsky
发明人： Albert Bergemont , Alexander Kalnitsky
IPC分类号： H01L31036
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A dielectric-based anti-fuse cell and cell array, that include a doped polysilicon contact plug, with a low resistance in the programmed state, a low capacitance, and a small cell area. The dielectric-based anti-fuse cell includes a first insulating layer, typically SiO2, on the surface of a semiconductor substrate. A first doped polysilicon (poly 1) layer is on the upper surface of the first insulating layer and a second insulating layer is over the poly 1 layer. A doped polysilicon contact plug extends through the second insulating layer and into the poly 1 layer. A dielectric layer, typically either an ONO or NO dielectric composite layer, covers the upper surface of the doped polysilicon contact plug. A second doped polysilicon (poly 2) layer is disposed on the dielectric layer. A process for manufacturing the anti-fuse cell and array includes first providing a semiconductor substrate and forming a first insulating layer on its surface. Next a poly 1 layer (e.g. bit lines) is formed on the surface of the first insulating layer followed by the formation of a second insulating layer over the poly 1 layer. A contact opening that extends into the poly 1 layer is then created in the second insulating layer and filled with a doped polysilicon contact plug. Next, a dielectric layer is formed on the upper surface of the doped polysilicon contact plug, followed by the formation of a poly 2 layer (e.g. word lines) on the upper surface of the dielectric layer.
摘要翻译：包括掺杂多晶硅接触插头的基于介质的反熔丝电池和电池阵列，其在编程状态下具有低电阻，低电容和小电池区。基于电介质的抗熔丝单元包括在半导体衬底的表面上的通常为SiO 2的第一绝缘层。第一掺杂多晶硅（poly 1）层位于第一绝缘层的上表面上，第二绝缘层在聚1层之上。掺杂多晶硅接触插塞延伸穿过第二绝缘层并进入聚1层。通常为ONO或NO电介质复合层的电介质层覆盖掺杂多晶硅接触插塞的上表面。第二掺杂多晶硅（poly 2）层设置在电介质层上。制造抗熔丝电池和阵列的方法包括首先提供半导体衬底并在其表面上形成第一绝缘层。接下来，在第一绝缘层的表面上形成聚1层（例如位线），然后在聚1层上形成第二绝缘层。然后在第二绝缘层中形成延伸到聚1层的接触开口，并填充掺杂的多晶硅接触插塞。接下来，在掺杂多晶硅接触插塞的上表面上形成电介质层，然后在电介质层的上表面上形成聚二层（例如字线）。

10. 发明授权

US06197671B1 Multiple finger polysilicon gate structure and method of making 有权
标题翻译：多指多晶硅门结构及其制作方法
公开(公告)号：US06197671B1
公开(公告)日：2001-03-06
申请号：US09132732
申请日：1998-08-12
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L213205
CPC分类号： H01L21/76895 , H01L21/823443 , H01L21/823456
摘要： Disclosed is a MOS transistor having a polysilicon gate structure in which an overlying metal interconnect completely shorts the gate area. In one embodiment, the gate is formed from multiple fingers joined in a serpentine pattern and separated by oxide-filled spaces. Overlying the fingers and oxide-filled spaces is an interconnect comprising a first metal layer and a second metal layer. The first metal layer overlies the fingers and oxide-filled spaces and the second metal layer overlies the first metal layer. Both metal layers form a stack that simultaneously shorts the fingers. Also disclosed is a method of fabricating such a polysilicon gate structure in a MOS transistor using a series of masks. Once the gate and fingers are defined, a conformal oxide is deposited over the fingers and in the spaces between the fingers. The conformal oxide is anisotropically etched to produce a planarized profile of the fingers and oxide-filled spaces. A metal interconnect is formed from a first metal layer and an overlying second metal layer by which all of the fingers are shorted simultaneously.
摘要翻译：公开了具有多晶硅栅极结构的MOS晶体管，其中上覆的金属互连完全使栅极区域短路。在一个实施例中，栅极由多个指状物形成，其以蛇形图案连接并被氧化物填充的空间分开。指状物和填充氧化物的空间覆盖着包括第一金属层和第二金属层的互连。第一金属层覆盖在手指和氧化物填充空间之间，第二金属层覆盖在第一金属层上。两个金属层形成一个同时使手指短路的叠层。还公开了使用一系列掩模在MOS晶体管中制造这种多晶硅栅极结构的方法。一旦门和手指被限定，保形氧化物沉积在手指之间和手指之间的空间中。各向异性蚀刻共形氧化物以产生手指和氧化物填充空间的平坦化轮廓。金属互连由第一金属层和上覆的第二金属层形成，通过该第二金属层，所有的指状物同时短路。

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