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1. 发明授权

US09459234B2 CMOS compatible BioFET 有权
标题翻译： CMOS兼容的BioFET
公开(公告)号：US09459234B2
公开(公告)日：2016-10-04
申请号：US13480161
申请日：2012-05-24
申请人： Alexander Kalnitsky , Yi-Shao Liu , Kai-Chih Liang , Chia-Hua Chu , Chun-Ren Cheng , Chun-Wen Cheng
发明人： Alexander Kalnitsky , Yi-Shao Liu , Kai-Chih Liang , Chia-Hua Chu , Chun-Ren Cheng , Chun-Wen Cheng
IPC分类号： H01L51/05 , G01N27/414 , H01L51/00
CPC分类号： G01N27/4145 , G01N27/414 , G01N27/4148 , H01L21/84 , H01L27/1203 , H01L51/0093
摘要： The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
摘要翻译：本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET器件可以包括衬底; 设置在基板的第一表面上的栅极结构和形成在基板的第二表面上的界面层。界面层可以允许将受体置于界面层上以检测生物分子或生物实体的存在。

2. 发明授权

US08723123B2 Light detector with Ge film 有权
标题翻译：光电探测器与Ge膜
公开(公告)号：US08723123B2
公开(公告)日：2014-05-13
申请号：US13595743
申请日：2012-08-27
申请人： Alexander Kalnitsky , Chia-Hua Chu , Fei-Lung Lai , Chun-Wen Cheng , Chun-Ren Cheng , Yi-Hsien Chang
发明人： Alexander Kalnitsky , Chia-Hua Chu , Fei-Lung Lai , Chun-Wen Cheng , Chun-Ren Cheng , Yi-Hsien Chang
IPC分类号： G01J5/20
CPC分类号： G01J1/1626 , G01J1/4204 , G01J3/465 , H01L31/02164 , H01L31/103 , H01L31/105
摘要： A light detector includes a first light sensor and a second light sensor to detect incident light. A Ge film is disposed over the first light sensor to pass infra-red (IR) wavelength light and to block visible wavelength light. The Ge film does not cover the second light sensor.
摘要翻译：光检测器包括第一光传感器和用于检测入射光的第二光传感器。将Ge膜设置在第一光传感器上以通过红外（IR）波长的光并阻挡可见波长的光。 Ge膜不覆盖第二个光传感器。

3. 发明申请

US20130307663A1 RESISTOR ARRANGEMENT AND METHOD OF USE 有权
标题翻译：电阻器布置和使用方法
公开(公告)号：US20130307663A1
公开(公告)日：2013-11-21
申请号：US13619225
申请日：2012-09-14
申请人： Alan ROTH , Alexander KALNITSKY , Chien-Chung TSENG
发明人： Alan ROTH , Alexander KALNITSKY , Chien-Chung TSENG
IPC分类号： H01C7/10
CPC分类号： H01C13/02 , H01C1/16
摘要： This disclosure relates to a semiconductor device including resistor arrangement including a first resistor electrically connected to a ground voltage and a second resistor in direct physical contact with the first resistor. The second resistor is configured to receive a temperature independent current and the second resistor has thermal properties similar to those of the first resistor. This disclosure also relates to a semiconductor device including a load configured to receive an operating voltage and a voltage source configured to supply the operating voltage. The semiconductor device further includes a resistor arrangement between the load and the voltage source. This disclosure also relates to a method of using a resistor arrangement to calculate an operating current.
摘要翻译：本公开涉及包括电阻器装置的半导体器件，该电阻器装置包括电连接到接地电压的第一电阻器和与第一电阻器直接物理接触的第二电阻器。第二电阻器被配置为接收与温度无关的电流，并且第二电阻器具有与第一电阻器类似的热特性。本公开还涉及包括被配置为接收工作电压的负载和被配置为提供工作电压的电压源的半导体器件。半导体器件还包括负载和电压源之间的电阻器配置。本公开还涉及使用电阻器装置来计算工作电流的方法。

4. 发明授权

US08101511B2 Method of manufacturing a junction barrier Schottky diode with dual silicides 有权
标题翻译：制造具有双重硅化物的结屏障肖特基二极管的方法
公开(公告)号：US08101511B2
公开(公告)日：2012-01-24
申请号：US12774762
申请日：2010-05-06
申请人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
发明人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译：包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。与第一硅化物不同的第二硅化物层位于阳极区上。对阳极区域和阱的第二硅化物进行欧姆接触。

5. 发明申请

US20110176368A1 MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE 有权
标题翻译：多通道时间可编程（MTP）PMOS浮动栅基非易失性存储器件用于一般用途CMOS技术与厚栅氧化物
公开(公告)号：US20110176368A1
公开(公告)日：2011-07-21
申请号：US13077065
申请日：2011-03-31
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04 , H01L29/94
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的扩展漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

6. 发明授权

US07903465B2 Memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的存储器阵列
公开(公告)号：US07903465B2
公开(公告)日：2011-03-08
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

7. 发明授权

US07768273B1 Electrostatic discharge protection of a capacitive type fingerprint sensing array 有权
标题翻译：电容型指纹感测阵列的静电放电保护
公开(公告)号：US07768273B1
公开(公告)日：2010-08-03
申请号：US12396102
申请日：2009-03-02
申请人： Alexander Kalnitsky , Alan Kramer
发明人： Alexander Kalnitsky , Alan Kramer
IPC分类号： G01R27/26
CPC分类号： H01L27/0248 , G06K9/00053
摘要： A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes a first capacitor plate placed vertically under the upper surface of a dielectric layer and a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate. Electrostatic discharge protection relative to electrostatic potential that may be carried by an ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.
摘要翻译：平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。每个感测单元包括垂直于电介质层的上表面放置的第一电容器板和垂直于电介质层的上表面放置在与第一电容器板紧密的水平空间关系的第二电容器板。通过在电介质层内放置多个接地的金属路径以空间地围绕第一和第二电容器板的每一个来提供相对于静电电位的静电放电保护，这是通过不接地的指尖承载的，这是以不是打扰指尖的未接地状态。

8. 发明授权

US07700977B2 Integrated circuit with a subsurface diode 失效
标题翻译：集成电路与地下二极管
公开(公告)号：US07700977B2
公开(公告)日：2010-04-20
申请号：US12037569
申请日：2008-02-26
申请人： Michael David Church , Alexander Kalnitsky , Lawrence George Pearce , Michael Ray Jayne , Thomas Andrew Jochum
发明人： Michael David Church , Alexander Kalnitsky , Lawrence George Pearce , Michael Ray Jayne , Thomas Andrew Jochum
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L27/0255 , H01L27/0814
摘要： An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.
摘要翻译：集成电路包括并联连接的第一和第二二极管。第一二极管具有第一击穿电压，并且在衬底的衬底的表面处具有彼此相邻的第一P型区域和第一N型区域，以形成横向二极管。第二二极管具有小于第一击穿电压的第二击穿电压，并且在衬底中具有彼此相邻的第二P型区域和第二N型区域，以在表面下方形成横向二极管。第一和第二N型区域重叠并且第一和第二P型区域电连接，由此第一和第二二极管是并联的。

9. 发明授权

US07522753B2 Electrostatic discharge protection of a capacitive type fingerprint sensing array 失效
标题翻译：电容型指纹感测阵列的静电放电保护
公开(公告)号：US07522753B2
公开(公告)日：2009-04-21
申请号：US11162861
申请日：2005-09-27
申请人： Alexander Kalnitsky , Alan Kramer
发明人： Alexander Kalnitsky , Alan Kramer
IPC分类号： G06K9/00
CPC分类号： G06F3/044 , G06F2203/04107 , G06K9/00053 , H01L27/0248
摘要： A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.
摘要翻译：平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。每个感测单元包括具有不接地输入模式的放大器和未接地输出节点。通过以下步骤为每个放大器提供对指纹图案敏感的输出到输入负反馈：（1）第一电容器板，其垂直放置在电介质层的上表面下方并连接到未接地的放大器输入节点，（2）第二电容器板，其垂直于电介质层的上表面放置在与第一电容器板紧密的水平空间关系上，并连接到未接地的输出节点，（3）指纹图案为未接地的指尖要被检测到，哪个未接地的指尖被放置在与第一和第二电容器板紧密垂直空间关系的电介质层的上表面上。通过在电介质层内放置多个接地的金属路径来空间地围绕第一和第二电容器板中的每一个来提供相对于静电电位的静电放电保护，这是通过不接地的指尖来承载的，打扰指尖的未接地状态。

10. 发明申请

US20080135968A1 LIGHT SENSORS WITH INFRARED SUPPRESSION 失效
标题翻译：具有红外抑制的光传感器
公开(公告)号：US20080135968A1
公开(公告)日：2008-06-12
申请号：US11621443
申请日：2007-01-09
申请人： Alexander Kalnitsky , Dong Zheng , Joy Jones , Xijian Lin , Gregory Cestra
发明人： Alexander Kalnitsky , Dong Zheng , Joy Jones , Xijian Lin , Gregory Cestra
IPC分类号： H01L31/02
CPC分类号： H01L31/103 , H01L27/1443 , H01L31/02162
摘要： Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.
摘要翻译：本发明的实施例涉及在抑制红外光的同时主要响应于可见光的光传感器。这种传感器作为环境光传感器是特别有用的，因为这样的传感器可用于提供类似于人眼的光谱响应。本发明的实施例还涉及提供这种光传感器的方法，以及使用这种光传感器的方法。

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