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1. 发明授权

US09023429B2 Method of manufacturing semiconductor device and substrate processing apparatus 有权
标题翻译：制造半导体器件和衬底处理设备的方法
公开(公告)号：US09023429B2
公开(公告)日：2015-05-05
申请号：US13626382
申请日：2012-09-25
申请人： Yuichiro Takeshima , Osamu Kasahara , Kazuyuki Toyoda , Junichi Tanabe , Katsuhiko Yamamoto , Hisashi Nomura
发明人： Yuichiro Takeshima , Osamu Kasahara , Kazuyuki Toyoda , Junichi Tanabe , Katsuhiko Yamamoto , Hisashi Nomura
IPC分类号： H01L21/02 , C23C16/00 , C23C16/56 , C23C16/54 , H01L21/67 , H01L21/687 , C23C16/44 , C23C16/46 , H01L21/683 , H01L21/677
CPC分类号： C23C16/54 , C23C16/4408 , C23C16/463 , H01L21/02164 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L21/67109 , H01L21/67754 , H01L21/68764 , H01L21/68771
摘要： A method of manufacturing a semiconductor device including: mounting a substrate on a substrate mounting member that is disposed in a reaction container; heating the substrate at a predetermined processing temperature and supplying a first gas and a second gas to the substrate to process the substrate; stopping supply of the first gas and the second gas, and supplying an inert gas into the reaction container; and unloading the substrate to outside the reaction container.
摘要翻译：一种制造半导体器件的方法，包括：将衬底安装在设置在反应容器中的衬底安装构件上; 在预定的处理温度下加热衬底并将第一气体和第二气体供应到衬底以处理衬底; 停止供应第一气体和第二气体，并将惰性气体供应到反应容器中; 并将基板卸载到反应容器外部。

2. 发明授权

US08293646B2 Semiconductor device manufacturing method and substrate processing apparatus 有权
标题翻译：半导体装置的制造方法和基板处理装置
公开(公告)号：US08293646B2
公开(公告)日：2012-10-23
申请号：US11667078
申请日：2005-11-02
申请人： Takashi Ozaki , Osamu Kasahara , Takaaki Noda , Kiyohiko Maeda , Atsushi Moriya , Minoru Sakamoto
发明人： Takashi Ozaki , Osamu Kasahara , Takaaki Noda , Kiyohiko Maeda , Atsushi Moriya , Minoru Sakamoto
IPC分类号： H01L21/02
CPC分类号： C23C16/54 , C23C16/4408 , C30B25/02 , C30B29/06 , H01L21/02046 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/67017 , H01L21/67109
摘要： A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.
摘要翻译：在基板和薄膜之间以低的氧 - 碳密度形成高质量的界面，同时防止对基板的热损伤并增加热预算。该方法包括将晶片装载到反应炉中的步骤，在反应炉中预处理晶片的步骤，在反应炉中进行预处理的晶片的主要处理的步骤，以及将晶片从反应炉主要加工后。在从预处理步骤结束到主处理开始的时段内，至少在反应炉内部真空排气期间，将氢气连续供给到反应炉。

3. 发明申请

US20120064733A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS 有权
标题翻译：制造半导体器件和衬底加工设备的方法
公开(公告)号：US20120064733A1
公开(公告)日：2012-03-15
申请号：US13227312
申请日：2011-09-07
申请人： Ryota SASAJIMA , Yoshiro HIROSE , Naonori AKAE , Osamu KASAHARA
发明人： Ryota SASAJIMA , Yoshiro HIROSE , Naonori AKAE , Osamu KASAHARA
IPC分类号： H01L21/31 , H01L21/306
CPC分类号： C23C16/345 , C23C16/401 , C23C16/45527 , C23C16/56
摘要： Provided is a method of manufacturing a semiconductor device, including: forming a silicon oxide film on a surface of a substrate holder by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer; forming a thin film on a substrate by using a process gas; removing deposits attached onto the substrate holder by using a fluorine-containing gas; and reforming a silicon oxide film on the surface of the substrate holder after removal of the deposits by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer by using an oxygen-containing gas and a hydrogen-containing gas.
摘要翻译：提供一种制造半导体器件的方法，包括：在衬底保持器的表面上重复地形成含硅层并氧化含硅层，在衬底保持器的表面上形成氧化硅膜; 通过使用工艺气体在衬底上形成薄膜; 通过使用含氟气体去除附着在基板支架上的沉积物; 以及通过在所述衬底保持器的表面上重复地形成含硅层并且通过使用含氧气体氧化所述含硅层并除去所述沉积物之后，在所述衬底保持器的表面上重整氧化硅膜含氢气体。

4. 发明申请

US20090117752A1 Semiconductor device manufacturing method and substrate processing apparatus 有权
标题翻译：半导体装置的制造方法和基板处理装置
公开(公告)号：US20090117752A1
公开(公告)日：2009-05-07
申请号：US11667078
申请日：2005-11-02
申请人： Takashi Ozaki , Osamu Kasahara , Takaaki Noda , Kiyohiko Maeda , Atsushi Moriya , Minoru Sakamoto
发明人： Takashi Ozaki , Osamu Kasahara , Takaaki Noda , Kiyohiko Maeda , Atsushi Moriya , Minoru Sakamoto
IPC分类号： H01L21/02 , F23N5/22
CPC分类号： C23C16/54 , C23C16/4408 , C30B25/02 , C30B29/06 , H01L21/02046 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/67017 , H01L21/67109
摘要： A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.
摘要翻译：在基板和薄膜之间以低的氧 - 碳密度形成高质量的界面，同时防止对基板的热损伤并增加热预算。该方法包括将晶片装载到反应炉中的步骤，在反应炉中预处理晶片的步骤，在反应炉中进行预处理的晶片的主要处理的步骤，以及将晶片从反应炉主要加工后。在从预处理步骤结束到主处理开始的时段内，至少在反应炉内部真空排气期间，将氢气连续供给到反应炉。

5. 发明授权

US06576063B2 Apparatus and method for use in manufacturing a semiconductor device 有权
公开(公告)号：US06576063B2
公开(公告)日：2003-06-10
申请号：US09768663
申请日：2001-01-24
申请人： Kazuyuki Toyoda , Osamu Kasahara , Tsutomu Tanaka , Mamoru Sueyoshi , Nobuhito Shima , Masanori Sakai
发明人： Kazuyuki Toyoda , Osamu Kasahara , Tsutomu Tanaka , Mamoru Sueyoshi , Nobuhito Shima , Masanori Sakai
IPC分类号： C23C1600
CPC分类号： C23C16/45563 , C23C16/452 , C23C16/56 , H01J37/32357 , H01L21/67069
摘要： An apparatus for use in manufacturing a semiconductor device allows one or more substrates treated substantially free of the metal particles released from the chamber wall and the high energy particles emitted from the plasma and also allows them to uniformly heated to a relatively high temperature. The apparatus comprises a reaction chamber wherein one or more substrates to be treated are disposed, a plasma source arranged outside of and in proximity to the reaction chamber, an active species supply port for providing active species generated by the plasma source to the reaction chamber and arranged at a side of the reaction chamber and an exhaust port provided at the opposite side to the active species supply port. The active species flows parallel to the surfaces of the substrates.

6. 发明授权

US5811316A Method of forming teos oxide and silicon nitride passivation layer on aluminum wiring 失效
标题翻译：在铝线上形成氧化硅和氮化硅钝化层的方法
公开(公告)号：US5811316A
公开(公告)日：1998-09-22
申请号：US460931
申请日：1995-06-05
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/28
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

7. 发明授权

US5331191A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US5331191A
公开(公告)日：1994-07-19
申请号：US954142
申请日：1992-09-30
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/10
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

8. 发明授权

US5060045A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5060045A
公开(公告)日：1991-10-22
申请号：US422640
申请日：1989-10-17
申请人： Nobuo Owada , Hiroyuki Akimori , Takahisa Nitta , Tohru Kobayashi , Shunji Sasabe , Mikinori Kawaji , Osamu Kasahara
发明人： Nobuo Owada , Hiroyuki Akimori , Takahisa Nitta , Tohru Kobayashi , Shunji Sasabe , Mikinori Kawaji , Osamu Kasahara
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/118
CPC分类号： H01L27/118
摘要： Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction. The wiring pitches of the second-layer wiring lines and the third-layer wiring lines are set substantially equal to or smaller than the wiring pitch of th first-layer wiring lines. As a further aspect of the present invention, the ratio of wiring pitch of third-layer wiring lines to first-layer wiring lines can be 0.5, 1.0, 1.5 or 2.0. In addition, insulator films on which are formed the wiring lines are respectively subjected to flattening processes in order to flatten their upper surfaces, prior to providing the wiring lines thereon.
摘要翻译：公开了一种采用门阵列方案的半导体集成电路装置，具有由设计自动化系统形成的多层布线。根据本发明的器件包括具有碱性电池形成区域的半导体衬底，所述碱性电池形成区域彼此间隔开，并且在相邻的基本电池形成区域之间具有布线沟道区域。布线至少包括布置在布线沟道区域上的第一层布线; 覆盖基本单元形成区域和布线沟道区域的第二层布线; 以及覆盖基本单元形成区域和布线沟道区域的第三层布线。第一，第二和第三层布线分别在第一，第二和第三方向上延伸，第二方向不同于第一方向。第二层布线和第三层布线的布线间距基本上等于或小于第一层布线的布线间距。作为本发明的另一方面，第三层布线与第一层布线的布线间距的比可以为0.5,1.0,1.5或2.0。此外，在其上形成布线的绝缘膜分别在其上提供布线之前分别进行平坦化处理以使其上表面变平。

9. 发明授权

US09096928B2 Method of manufacturing semiconductor device and substrate processing apparatus 有权
标题翻译：制造半导体器件和衬底处理设备的方法
公开(公告)号：US09096928B2
公开(公告)日：2015-08-04
申请号：US13227312
申请日：2011-09-07
申请人： Ryota Sasajima , Yoshiro Hirose , Naonori Akae , Osamu Kasahara
发明人： Ryota Sasajima , Yoshiro Hirose , Naonori Akae , Osamu Kasahara
IPC分类号： H01L21/00 , C23C16/34 , C23C16/40 , C23C16/455 , C23C16/56
CPC分类号： C23C16/345 , C23C16/401 , C23C16/45527 , C23C16/56
摘要： Provided is a method of manufacturing a semiconductor device, including: forming a silicon oxide film on a surface of a substrate holder by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer; forming a thin film on a substrate by using a process gas; removing deposits attached onto the substrate holder by using a fluorine-containing gas; and reforming a silicon oxide film on the surface of the substrate holder after removal of the deposits by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer by using an oxygen-containing gas and a hydrogen-containing gas.
摘要翻译：提供一种制造半导体器件的方法，包括：在衬底保持器的表面上重复地形成含硅层并氧化含硅层，在衬底保持器的表面上形成氧化硅膜; 通过使用工艺气体在衬底上形成薄膜; 通过使用含氟气体去除附着在基板支架上的沉积物; 以及通过在所述衬底保持器的表面上重复地形成含硅层并且通过使用含氧气体氧化所述含硅层并除去所述沉积物之后，在所述衬底保持器的表面上重整氧化硅膜含氢气体。

10. 发明授权

US6127255A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US6127255A
公开(公告)日：2000-10-03
申请号：US943729
申请日：1997-10-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/4763 , H01L21/469
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由元件分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的有源区的主表面上形成MISFET。所公开的方法包括在包括最上面布线的布线上形成绝缘膜，最上面的布线在相邻最上布线之间具有间隙。绝缘膜包括在布线和相邻的最上布线之间的间隙中形成氧化硅膜，并且在氧化硅膜上形成氮化硅膜，通过等离子体化学气相沉积形成氮化硅膜。氧化硅膜形成为具有至少相邻最上面布线之间的间隙的一半的厚度，其中氮化硅膜比氧化硅膜厚。

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