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    • 8. 发明授权
    • Semiconductor integrated circuit device and method of manufacturing the
same
    • 半导体集成电路器件及其制造方法
    • US5060045A
    • 1991-10-22
    • US422640
    • 1989-10-17
    • Nobuo OwadaHiroyuki AkimoriTakahisa NittaTohru KobayashiShunji SasabeMikinori KawajiOsamu Kasahara
    • Nobuo OwadaHiroyuki AkimoriTakahisa NittaTohru KobayashiShunji SasabeMikinori KawajiOsamu Kasahara
    • H01L21/3205H01L21/82H01L23/52H01L27/118
    • H01L27/118
    • Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction. The wiring pitches of the second-layer wiring lines and the third-layer wiring lines are set substantially equal to or smaller than the wiring pitch of th first-layer wiring lines. As a further aspect of the present invention, the ratio of wiring pitch of third-layer wiring lines to first-layer wiring lines can be 0.5, 1.0, 1.5 or 2.0. In addition, insulator films on which are formed the wiring lines are respectively subjected to flattening processes in order to flatten their upper surfaces, prior to providing the wiring lines thereon.
    • 公开了一种采用门阵列方案的半导体集成电路装置,具有由设计自动化系统形成的多层布线。 根据本发明的器件包括具有碱性电池形成区域的半导体衬底,所述碱性电池形成区域彼此间隔开,并且在相邻的基本电池形成区域之间具有布线沟道区域。 布线至少包括布置在布线沟道区域上的第一层布线; 覆盖基本单元形成区域和布线沟道区域的第二层布线; 以及覆盖基本单元形成区域和布线沟道区域的第三层布线。 第一,第二和第三层布线分别在第一,第二和第三方向上延伸,第二方向不同于第一方向。 第二层布线和第三层布线的布线间距基本上等于或小于第一层布线的布线间距。 作为本发明的另一方面,第三层布线与第一层布线的布线间距的比可以为0.5,1.0,1.5或2.0。 此外,在其上形成布线的绝缘膜分别在其上提供布线之前分别进行平坦化处理以使其上表面变平。