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1. 发明授权

US5060045A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5060045A
公开(公告)日：1991-10-22
申请号：US422640
申请日：1989-10-17
申请人： Nobuo Owada , Hiroyuki Akimori , Takahisa Nitta , Tohru Kobayashi , Shunji Sasabe , Mikinori Kawaji , Osamu Kasahara
发明人： Nobuo Owada , Hiroyuki Akimori , Takahisa Nitta , Tohru Kobayashi , Shunji Sasabe , Mikinori Kawaji , Osamu Kasahara
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/118
CPC分类号： H01L27/118
摘要： Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction. The wiring pitches of the second-layer wiring lines and the third-layer wiring lines are set substantially equal to or smaller than the wiring pitch of th first-layer wiring lines. As a further aspect of the present invention, the ratio of wiring pitch of third-layer wiring lines to first-layer wiring lines can be 0.5, 1.0, 1.5 or 2.0. In addition, insulator films on which are formed the wiring lines are respectively subjected to flattening processes in order to flatten their upper surfaces, prior to providing the wiring lines thereon.
摘要翻译：公开了一种采用门阵列方案的半导体集成电路装置，具有由设计自动化系统形成的多层布线。根据本发明的器件包括具有碱性电池形成区域的半导体衬底，所述碱性电池形成区域彼此间隔开，并且在相邻的基本电池形成区域之间具有布线沟道区域。布线至少包括布置在布线沟道区域上的第一层布线; 覆盖基本单元形成区域和布线沟道区域的第二层布线; 以及覆盖基本单元形成区域和布线沟道区域的第三层布线。第一，第二和第三层布线分别在第一，第二和第三方向上延伸，第二方向不同于第一方向。第二层布线和第三层布线的布线间距基本上等于或小于第一层布线的布线间距。作为本发明的另一方面，第三层布线与第一层布线的布线间距的比可以为0.5,1.0,1.5或2.0。此外，在其上形成布线的绝缘膜分别在其上提供布线之前分别进行平坦化处理以使其上表面变平。

2. 发明授权

US4819054A Semiconductor IC with dual groove isolation 失效
标题翻译：半导体IC双沟槽隔离
公开(公告)号：US4819054A
公开(公告)日：1989-04-04
申请号：US11932
申请日：1987-02-06
申请人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
发明人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
IPC分类号： H01L21/762 , H01L21/763 , H01L29/732 , H01L27/12
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7325 , Y10S148/05
摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.
摘要翻译：双极型半导体集成电路器件设置有通过切割半导体本体的主表面以在双极晶体管之间形成隔离区而形成的U形沟槽。可以通过热氧化在U形槽中形成氧化硅膜，同时形成用于在每个集电极接触区域和基极区域之间形成隔离区域的氧化硅膜。在集电极接触区域和基极区域之间形成氧化硅膜不需要单独的步骤。可以控制氧化硅膜的厚度，并且即使在其两个边缘，即与U形槽的边界处，也具有足够的厚度，使得双极晶体管表现出良好的电特性。也就是说，其集电极电阻不增加，并且集电极区域和基极区域之间的pn结处的击穿电压不降低。 U形槽可以各自包括窄的和深的子槽，其中形成在子槽的表面上的厚的氧化膜和形成在子槽之间的区域的表面上的厚氧化膜，并且形成有布线在子槽之间的区域上的氧化物上。

3. 发明授权

US5117277A Semiconductor integrated circuit device with improved connection pattern of signal wirings 失效
标题翻译：具有改善的信号布线连接方式的半导体集成电路器件
公开(公告)号：US5117277A
公开(公告)日：1992-05-26
申请号：US469397
申请日：1990-01-24
申请人： Kyoji Yuyama , Mikinori Kawaji
发明人： Kyoji Yuyama , Mikinori Kawaji
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/485 , H01L23/52 , H01L23/528
CPC分类号： H01L24/06 , H01L23/528 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/1305 , H01L2924/14
摘要： A semiconductor integrated circuit device having a plurality of first wirings that are formed on a semiconductor substrate and extend in a first direction and a plurality of second wirings that extend in a second direction defining an acute angle relative to the first direction. The plurality of first and second wirings have at their ends connection portions of a regular hexagonal shape or a circular shape.
摘要翻译：一种半导体集成电路器件，具有形成在半导体衬底上并沿第一方向延伸的多个第一配线以及沿相对于第一方向限定锐角的第二方向延伸的多个第二配线。多个第一和第二布线在其端部具有正六边形形状或圆形形状的连接部分。

4. 发明授权

US5342480A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US5342480A
公开(公告)日：1994-08-30
申请号：US069844
申请日：1993-06-01
申请人： Hirotaka Nishizawa , Seiichiro Azuma , Takayuki Yoshitake , Kazuo Tanaka , Mikinori Kawaji , Sinmei Hirano , Toshio Yamada , Yasusi Sekine
发明人： Hirotaka Nishizawa , Seiichiro Azuma , Takayuki Yoshitake , Kazuo Tanaka , Mikinori Kawaji , Sinmei Hirano , Toshio Yamada , Yasusi Sekine
IPC分类号： H01L21/265 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/8248 , H01L27/108 , H01L27/12 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/786 , H01L21/306 , B44C1/22
CPC分类号： H01L21/76229 , H01L21/8248 , H01L27/10829
摘要： An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed. The technique includes forming grooves, to the main surface of a non-active region of a semiconductor substrate or a semiconductor layer, each groove extending into the substrate or layer and forming island regions of the substrate or layer, forming a burying material and a first mask having an etching rate greater than that of the burying material successively over the entire surface of the semiconductor substrate or the semiconductor layer including areas on the upper surface of the island regions and in the grooves, such that the film thickness is made virtually uniform for each of the surfaces, forming a second mask on the surface of the first mask, through which the region on each of the island regions is exposed and in which the end of the opening is situated from the end of the island region to the outside of the island region within a distance 0.7 times of the film thickness for the sum of the burying material and the first mask, and applying isotropic etching successively to each of the first mask and the burying material by using the second mask as an etching mask, under a condition in which the etching rate for the first mask is greater than that for the burying material.
摘要翻译：公开了一种在其上形成有半导体衬底的隔离和平坦化技术，其具有诸如双极晶体管和MISFET之类的有源器件。该技术包括在半导体衬底或半导体层的非有源区的主表面上形成凹槽，每个凹槽延伸到衬底或层中并形成衬底或层的岛区，形成掩埋材料和第一在半导体衬底或半导体层的整个表面上连续地具有大于掩埋材料的蚀刻速率的掩模，该蚀刻速率包括在岛状区域和沟槽的上表面上的区域，使得膜厚实质上是均匀的每个所述表面在所述第一掩模的表面上形成第二掩模，所述岛状区域中的所述区域通过所述第二掩模暴露，并且所述开口的所述端部从所述岛状区域的所述端部位于所述岛状区域的外部在距离掩模材料和第一掩模的总和的膜厚的0.7倍的范围内的岛区域，并且将各向同性蚀刻连续地施加到e 在第一掩模的蚀刻速率大于掩埋材料的蚀刻速率的条件下，通过使用第二掩模作为蚀刻掩模，在第一掩模和掩埋材料的掩模之间。

5. 发明授权

US5011788A Process of manufacturing semiconductor integrated circuit device and product formed thereby 失效
标题翻译：制造半导体集成电路器件的工艺和由此形成的产品
公开(公告)号：US5011788A
公开(公告)日：1991-04-30
申请号：US284557
申请日：1988-12-15
申请人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
发明人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
IPC分类号： H01L21/762 , H01L21/763 , H01L29/732
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7325 , Y10S148/05
摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

6. 发明授权

US5306948A Semiconductor device and semiconductor module having auxiliary high power supplying terminals 失效
标题翻译：具有辅助高功率供电端子的半导体器件和半导体模块
公开(公告)号：US5306948A
公开(公告)日：1994-04-26
申请号：US950332
申请日：1992-09-24
申请人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
发明人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
IPC分类号： H01L21/66 , G01R1/04 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/498 , H01L25/065 , H01L23/02 , H01L23/12
CPC分类号： H01L25/0655 , G01R1/0483 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/49805 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152
摘要： Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.
摘要翻译：这里公开的是采用MCC结构的芯片载体型半导体器件，其中半导体芯片安装在基底表面上，并且其中与半导体芯片的外部端子连接的安装端子安装在后表面的基底。即使安装端子倍增或小型化，为了实现轻松便宜地进行测试，采用MCC结构的芯片载体型半导体器件配置在具有辅助端子的基底基板的电连接多个外部端子排列在半导体芯片的形成元件的主表面上。

7. 发明授权

US5220199A Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate 失效
标题翻译：半导体集成电路器件，其中半导体芯片安装有用于安装到布线基板的焊料凸块
公开(公告)号：US5220199A
公开(公告)日：1993-06-15
申请号：US714627
申请日：1991-06-13
申请人： Nobuo Owada , Kaoru Oogaya , Tohru Kobayashi , Mikinori Kawaji
发明人： Nobuo Owada , Kaoru Oogaya , Tohru Kobayashi , Mikinori Kawaji
IPC分类号： H01L23/485 , H01L23/498
CPC分类号： H01L23/49816 , H01L24/05 , H01L2224/02235 , H01L2224/02255 , H01L2224/0401 , H01L2224/05556 , H01L2224/05558 , H01L2224/13027 , H01L2224/131 , H01L2224/16 , H01L2224/73253 , H01L24/13 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/19043 , H01L2924/30105
摘要： A multi-layered structure of wirings on a semiconductor substrate has been employed in conjunction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.
摘要翻译：结合半导体集成电路器件的集成密度的增加，已经采用半导体衬底上的布线的多层结构。在本发明中，为了减少凸起电极下方的区域和附近的区域，设置由与Al布线层相同的材料制成的用于补偿任何阶梯或等级的虚拟图案，以便减少多层结构固有的缺陷发生在形成在多层布线上的CCB凸起电极和作为前者的基底层的焊盘处。

8. 发明授权

US5141888A Process of manufacturing semiconductor integrated circuit device having trench and field isolation regions 失效
标题翻译：制造具有TRENCH和现场隔离区域的半导体集成电路装置的制造方法
公开(公告)号：US5141888A
公开(公告)日：1992-08-25
申请号：US642922
申请日：1991-01-18
申请人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
发明人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
IPC分类号： H01L21/762 , H01L21/763 , H01L29/732
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7325 , Y10S148/05
摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

9. 发明授权

US5027188A Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate 失效
标题翻译：半导体集成电路器件，其中半导体芯片安装有用于安装到布线基板的焊料凸块
公开(公告)号：US5027188A
公开(公告)日：1991-06-25
申请号：US406548
申请日：1989-09-13
申请人： Nobuo Owada , Kaoru Oogaya , Tohru Kobayashi , Mikinori Kawaji
发明人： Nobuo Owada , Kaoru Oogaya , Tohru Kobayashi , Mikinori Kawaji
IPC分类号： H01L21/60 , H01L23/485 , H01L23/498
CPC分类号： H01L24/05 , H01L23/49816 , H01L24/13 , H01L2224/0401 , H01L2224/05556 , H01L2224/13027 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16238 , H01L2224/73253 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/19043 , H01L2924/30105
摘要： A multi-layered structure of wirings on a semiconductor substrate has been employed in conjuction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.
摘要翻译：结合半导体集成电路器件的集成密度的增加，已经采用半导体衬底上的布线的多层结构。在本发明中，为了减少凸起电极下方的区域和附近的区域，设置由与Al布线层相同的材料制成的用于补偿任何阶梯或等级的虚拟图案，以便减少多层结构固有的缺陷发生在形成在多层布线上的CCB凸起电极和作为前者的基底层的焊盘处。

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