专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08094754B2 Frequency hold mechanism in a clock and data recovery device 有权
标题翻译：时钟和数据恢复设备中的频率保持机制
公开(公告)号：US08094754B2
公开(公告)日：2012-01-10
申请号：US12327776
申请日：2008-12-03
申请人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
发明人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
IPC分类号： H03D3/24
CPC分类号： H04L7/033 , H03L7/087 , H03L7/10 , H03L7/1976 , H03L7/22
摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

2. 发明申请

US20090147901A1 Auto Frequency Acquisition Maintenance in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的自动采集维护
公开(公告)号：US20090147901A1
公开(公告)日：2009-06-11
申请号：US12372946
申请日：2009-02-18
申请人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
发明人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
IPC分类号： H04L7/00
CPC分类号： H04L7/0331 , H03L7/0891 , H03L7/095 , H03L7/113 , H03L7/1976 , H04L7/0004
摘要： A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.
摘要翻译：提供了一种用于时钟和数据恢复（CDR）设备中的自动频率采集维护的系统和方法。在自动频率采集（AFA）模式中，该方法使用相位检测器（PHD）来获取具有初始第一频率的非同步输入通信信号的相位。在信号失去锁定/丢失（LOL / LOS）信号被断言的情况下，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生合成信号。响应于使用PFD产生合成信号并且LOL / LOS信号被无效，旋转频率检测器（RFD）用于产生具有等于输入通信信号频率的频率的合成信号。随着LOL / LOS信号的持续消除，PHD被使能，并且获取输入信号的相位。

3. 发明申请

US20090092213A1 Frequency Hold Mechanism in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的频率保持机制
公开(公告)号：US20090092213A1
公开(公告)日：2009-04-09
申请号：US12327776
申请日：2008-12-03
申请人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
发明人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
IPC分类号： H04L7/04
CPC分类号： H04L7/033 , H03L7/087 , H03L7/10 , H03L7/1976 , H03L7/22
摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

4. 发明授权

US07292667B1 Method and system for transmitting synchronization information with data 失效
标题翻译：用数据传输同步信息的方法和系统
公开(公告)号：US07292667B1
公开(公告)日：2007-11-06
申请号：US08220953
申请日：1994-03-31
申请人： Walter Joseph Beriont , Mehmet Mustafa
发明人： Walter Joseph Beriont , Mehmet Mustafa
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H03K5/135 , H04J3/0605 , H04J3/07
摘要： A method for transmitting synchronization information with data, which data corresponds to a sequence of samples representative of a signal, includes detecting the occurrence of two consecutive equivalent samples and inserting a synchronization pattern for the second-occurring sample prior to transmission. At a receiving end, the incoming signal is monitored to detect the presence of the sync pattern and hold the value of the receiver output at the value of the immediately previous received sample. In this manner, the signal is reconstructed without degradation, and byte synchronization information is sent without any bandwidth loss.
摘要翻译：一种用于发送具有数据的同步信息的方法，所述数据对应于表示信号的采样序列，包括检测两个连续等效样本的出现，并在发送之前插入第二次发生的样本的同步模式。在接收端，监视输入信号以检测同步模式的存在，并将接收机输出的值保持在紧接在前的接收样本的值。以这种方式，信号被重建而不劣化，并且发送字节同步信息而没有任何带宽损失。

5. 发明授权

US06876263B1 Dual voltage-controlled oscillator structure with powder-down feature 有权
标题翻译：双压控振荡器结构，具有粉碎功能
公开(公告)号：US06876263B1
公开(公告)日：2005-04-05
申请号：US10382638
申请日：2003-03-05
申请人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
发明人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
IPC分类号： H03B1/00 , H03B27/00
CPC分类号： H03B5/06 , H03B2200/0048
摘要： A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.
摘要翻译：压控振荡器（“VCO”）结构包括多个VCO电路，每个VCO电路具有不同的额定工作频率范围。通过各个VCO电路的选择性激活/去激活来调节VCO结构的功耗。在优选实施例中，在任何给定时间只有一个VCO电路是有效的。可以选择有源VCO以满足特定应用的要求和/或补偿半导体制造工艺变化。

6. 发明授权

US06566967B1 Configurable triple phase-locked loop circuit and method 有权
标题翻译：可配置三相锁相环电路及方法
公开(公告)号：US06566967B1
公开(公告)日：2003-05-20
申请号：US10085458
申请日：2002-02-26
申请人： Sudhaker Reddy Anumula , Joseph J. Balardeta , Wei Fu , Paul Vanderbilt , Mehmet Mustafa Eker
发明人： Sudhaker Reddy Anumula , Joseph J. Balardeta , Wei Fu , Paul Vanderbilt , Mehmet Mustafa Eker
IPC分类号： H03L700
CPC分类号： H03L7/18 , H03L7/087 , H03L7/0891 , H03L7/107 , H03L7/113 , H03L7/14
摘要： A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.
摘要翻译：具有多个检测元件的可配置PLL架构。可配置PLL电路包括用于提供第一差分信号的第一检测器，用于提供第二差分信号的第二检测器，用于提供第三差分信号的第三检测器，以及用于使第一，第二和第第三检测器。 PLL电路还包括多路复用器，用于从相应的使能检测器接收至少一个差分信号，并提供多路复用的差分信号输出。在操作中，选择操作模式，并且启用一个或多个检测器以使用一个或多个输入参考信号进行操作。使能的检测器的输出由多路复用器接收以完成所选择的操作模式的操作。

7. 发明授权

US08358159B1 Adaptive phase-locked loop (PLL) multi-band calibration 有权
标题翻译：自适应锁相环（PLL）多频带校准
公开(公告)号：US08358159B1
公开(公告)日：2013-01-22
申请号：US13045032
申请日：2011-03-10
申请人： Mehmet Mustafa Eker , Viet Do , Simon Pang
发明人： Mehmet Mustafa Eker , Viet Do , Simon Pang
IPC分类号： H03L7/06
CPC分类号： H03L7/095
摘要： Adaptive multi-band frequency calibration is provided for a phase-locked loop (PLL). A voltage controller oscillator (VCO) is initially selected nominally associated with first synthesized signal frequency, where the VCO is selected from a plurality of n VCOs, and each VCO is tunable across a band of synthesized signal frequencies. A lock detector compares a nominal first synthesized signal frequency to a reference signal frequency. In response to sensing a difference between the nominal first synthesizer and reference signal frequencies, an out-of-lock condition is asserted and a VCO is reselected from the plurality of n VCOs. A mid-point control voltage is supplied to a control voltage input of the reselected VCO. A difference is measured between a mid-point synthesized signal frequency and the reference signal frequency. If the difference is less than a first threshold, the reselected VCO is assigned to generate the first synthesized signal frequency.
摘要翻译：为锁相环（PLL）提供自适应多频带频率校准。最初选择与第一合成信号频率相关联的电压控制器振荡器（VCO），其中从多个n个VCO选择VCO，并且每个VCO可跨越合成信号频率的频带进行可调。锁定检测器将标称第一合成信号频率与参考信号频率进行比较。响应于感测标称第一合成器和参考信号频率之间的差异，断言失锁状态并且从多个n个VCO重新选择VCO。中点控制电压被提供给重新选择的VCO的控制电压输入。在中点合成信号频率和参考信号频率之间测量差异。如果差值小于第一阈值，则重新选择的VCO被分配以产生第一合成信号频率。

8. 发明授权

US08059778B1 Automatic clock frequency acquisition 有权
标题翻译：自动时钟频率采集
公开(公告)号：US08059778B1
公开(公告)日：2011-11-15
申请号：US12755292
申请日：2010-04-06
申请人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
发明人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
IPC分类号： H03D3/24
CPC分类号： H03L7/113 , H03L7/093 , H03L7/0995 , H03L7/1974 , H04L7/033 , H04L7/0331
摘要： A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer ≧1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1=Fref1/(x−1).
摘要翻译：提供了一种用于自动获取串行数据流时钟的系统和方法。该方法接收到具有未知时钟频率的串行数据流，并粗略地确定时钟频率。通过（最初）选择高频第一参考时钟（Fref1）粗略地确定频率，并且以等于Fref1 / n的多个采样频率对串行数据流的第一时间段中的数据转换次数进行计数，其中 n为整数≧1。将每个采样频率的计数与Fref1（n = 1）的计数进行比较。接下来，确定最高采样频率（n = x），其具有比Fref1更低的计数，并且将粗略时钟频率设置为Fc1 = Fref1 /（x-1）。

9. 发明授权

US07720189B2 System and method for automatic clock frequency acquisition 有权
标题翻译：自动时钟频率采集的系统和方法
公开(公告)号：US07720189B2
公开(公告)日：2010-05-18
申请号：US11595012
申请日：2006-11-09
申请人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
发明人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
IPC分类号： H03D3/24
CPC分类号： H03L7/113 , H03L7/093 , H03L7/0995 , H03L7/1974 , H04L7/033 , H04L7/0331
摘要： A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer≧1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1 =Fref1/(x−1).
摘要翻译：提供了一种用于自动获取串行数据流时钟的系统和方法。该方法接收到具有未知时钟频率的串行数据流，并粗略地确定时钟频率。通过（最初）选择高频第一参考时钟（Fref1）粗略地确定频率，并且以等于Fref1 / n的多个采样频率对串行数据流的第一时间段中的数据转换次数进行计数，其中 n为整数≧1。将每个采样频率的计数与Fref1（n = 1）的计数进行比较。接下来，确定最高采样频率（n = x），其具有比Fref1更低的计数，并且将粗略时钟频率设置为Fc1 = Fref1 /（x-1）。

10. 发明授权

US07692458B1 Wide dynamic range charge pump 有权
标题翻译：宽动态范围电荷泵
公开(公告)号：US07692458B1
公开(公告)日：2010-04-06
申请号：US12249915
申请日：2008-10-11
申请人： Mehmet Mustafa Eker
发明人： Mehmet Mustafa Eker
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03L7/0896 , H03L7/0893
摘要： A wide dynamic range charge pump is provided for use in a phase-locked loop (PLL) circuit. The charge pump includes a first, second, and third set of current sources. The charge pump further includes a first capacitor having an input connected to the first set. A first operational amplifier (op amp) has an input connected to the first set output, and an output connected to the second set output and to a voltage controlled oscillator (VCO) input. A first resistor has a first end connected to the first op amp output and a second end connected to the third set. A second capacitor has an input connected to the first resistor second end, and an output connected to the second reference voltage.
摘要翻译：提供了宽动态范围电荷泵，用于锁相环（PLL）电路。电荷泵包括第一，第二和第三组电流源。电荷泵还包括具有连接到第一组的输入端的第一电容器。第一运算放大器（运算放大器）具有连接到第一组输出的输入端和连接到第二组输出和压控振荡器（VCO）输入的输出。第一电阻器具有连接到第一运算放大器输出的第一端和连接到第三组的第二端。第二电容器具有连接到第一电阻器第二端的输入端和连接到第二参考电压的输出端。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式