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    • 4. 发明授权
    • GMP mapping method and apparatus for optical channel data unit
    • 用于光通道数据单元的GMP映射方法和装置
    • US09503191B2
    • 2016-11-22
    • US14396958
    • 2012-04-26
    • Shangqing WuTong WangYingfei LiZhangbin Lu
    • Shangqing WuTong WangYingfei LiZhangbin Lu
    • H04J3/02H04B10/27H04J3/16H04J3/07
    • H04B10/27H04J3/02H04J3/07H04J3/1652
    • The disclosure discloses a Generic Mapping Procedure (GMP) mapping method for an Optical channel Data Unit (ODU), including: caching low-level ODUk data to a memory according to the rate of low-level ODUk data stream; generating an adjustment byte in a mapping process and encoding the adjustment byte; generating read enable of the cached data by an algorithm according to the adjustment byte, reading the cached low-level ODUk data, and generating Optical channel Data Tributary Unit (ODTU) data according to the read data; and crossing a time slot of the ODTU data in multiple channels to that of a high-level ODU payload, and forming the data in the time slot of the high-level ODU payload and the encoded adjustment byte into a completed high-level ODU frame. The disclosure may further provide a GMP mapping apparatus for an ODU. According to a technical solution of the disclosure, the GMP mapping of the ODU can be implemented according to the dynamic change of a service rate.
    • 本公开公开了一种用于光信道数据单元(ODU)的通用映射过程(GMP)映射方法,包括:根据低级ODUk数据流的速率将低级ODUk数据缓存到存储器; 在映射过程中生成调整字节并对调整字节进行编码; 通过根据调整字节的算法生成缓存数据的读取使能,读取缓存的低级ODUk数据,以及根据读取的数据生成光信道数据支路单元(ODTU)数据; 并且将多个信道中的ODTU数据的时隙与高级ODU有效载荷的时隙交叉,并将高级ODU有效载荷和编码调整字节的时隙中的数据形成为完成的高级ODU帧 。 本公开还可以提供用于ODU的GMP映射设备。 根据本公开的技术方案,ODU的GMP映射可以根据业务速率的动态变化来实现。
    • 6. 发明申请
    • OPTICAL RECEIVER AND METHOD OF OPTICAL RECEPTION
    • 光接收器和光接收方法
    • US20150249506A1
    • 2015-09-03
    • US14606490
    • 2015-01-27
    • FUJITSU LIMITED
    • Hiroyuki KitajimaTakashi Kuwabara
    • H04B10/61
    • H04J3/1652H04B10/00H04J3/0623H04J3/07H04J3/085H04J3/14H04J3/167
    • An optical receiver includes a reception module, a first detector, a second detector, a shift module, a first extraction module, and a second extraction module. The reception module receives a frame. The first detector detects a head position of a first layer, the head position being included in the frame. The second detector detects a head position of a second layer, the head position being included in the frame. The shift module shifts the frame so that the head position of the first layer and the head position of the second layer are located at respective predetermined positions. The first extraction module extracts a header of the first layer from the frame after the frame is shifted. The second extraction module extracts a header of the second layer from the frame after the frame is shifted.
    • 光接收机包括接收模块,第一检测器,第二检测器,移位模块,第一提取模块和第二提取模块。 接收模块接收帧。 第一检测器检测第一层的头部位置,头部位置被包括在框架中。 第二检测器检测第二层的头部位置,头部位置被包括在框架中。 移位模块移动框架,使得第一层的头部位置和第二层的头部位置位于相应的预定位置。 第一提取模块在帧被移位之后从帧中提取第一层的标题。 第二提取模块在帧被移位之后从帧中提取第二层的标题。
    • 7. 发明授权
    • Data receiver, clock generation device, and method for controlling data receiver
    • 数据接收机,时钟生成装置及控制数据接收机的方法
    • US09098199B2
    • 2015-08-04
    • US14016675
    • 2013-09-03
    • FUJITSU LIMITED
    • Hideyuki MatsuuraHironobu Hongou
    • H03D3/24G06F5/06H04L7/033
    • G06F5/06H04J3/07H04L7/033H04L7/0331
    • A data receiver includes a writing unit that receives transmission data including live data and excessive data for adjusting a signal length to store the live data in a storage unit, an AND circuit that generates a first signal indicating the positions of the live data and the excessive data in the signal length of the transmission data, a signal converting unit that generates a second signal indicating positions at which positions of the excessive data in the first signal are rearranged at certain intervals in the signal length, a digital phase locked loop (DPLL) unit that smoothes the positions of the live data in the second signal to generate a third signal indicating the timing to read the live data in the signal length, and a reading unit that reads the live data stored in the storage unit by using the third signal.
    • 数据接收机包括:写入单元,其接收包括实时数据的发送数据和用于调整存储单元中的实时数据的信号长度的过多数据; AND电路,其生成指示实时数据的位置的第一信号和过量的 信号转换单元,其产生指示第一信号中的过量数据的位置在信号长度中以特定间隔重新排列的位置的第二信号;数字锁相环(DPLL) 单元,其使所述第二信号中的实时数据的位置平滑,以产生指示以所述信号长度读取实时数据的定时的第三信号;以及读取单元,其通过使用所述第三信号读取存储在所述存储单元中的实况数据 。
    • 9. 发明申请
    • TRANSMISSION METHOD, TRANSMISSION EQUIPMENT AND TRANSMISSION SYSTEM
    • 传输方法,传输设备和传输系统
    • US20140226981A1
    • 2014-08-14
    • US14148940
    • 2014-01-07
    • FUJITSU LIMITED
    • Takashi KUWABARA
    • H04B10/27
    • H04B10/27H04B10/00H04B10/61H04J3/07H04J3/1652
    • A transmission method that transmits an optical signal via a plurality of virtual lanes in dual polarization or multi-level modulation includes: receiving a first frame signal of a first frequency and a second frame signal of a second frequency, and storing the first and second frame signals on a memory; reading out the first frame signal from the memory at a third frequency, and inserting a stuff into the first frame signal such that a difference between the first frequency and the third frequency is adjusted to generate a third frame signal; reading out the second frame signal from the memory at the third frequency, and inserting a staff into the second frame signal such that a difference between the second frequency and the third frequency is adjusted to generate a fourth frame signal; and transmitting the third and fourth frame signals respectively via different virtual lanes.
    • 一种在双极化或多电平调制中通过多个虚拟通道发送光信号的传输方法包括:接收第一频率的第一帧信号和第二频率的第二帧信号,并存储第一和第二帧 记忆上的信号; 以第三频率从存储器读出第一帧信号,并且将第一帧频信号中的第一频率和第三频率之间的差值插入到第一帧信号中以产生第三帧信号; 以第三频率从存储器读出第二帧信号,并将人员插入到第二帧信号中,使得调整第二频率和第三频率之间的差以产生第四帧信号; 以及分别经由不同的虚拟通道发送第三和第四帧信号。
    • 10. 发明授权
    • Asynchronous line interface rate adaptation to the physical layer with synchronous lines at the connection layer
    • 异步线路接口速率适应物理层与同步线在连接层
    • US08711889B2
    • 2014-04-29
    • US12888522
    • 2010-09-23
    • Sergio LanzoneOrazio Toscano
    • Sergio LanzoneOrazio Toscano
    • H04J3/02
    • H04J3/12H04J3/0632H04J3/07H04L7/005H04L7/02H04L69/324H04L2007/045
    • A method for adapting the rates of a certain number of asynchronous HDLC channels (15) to a single clock domain suited for interfacing with an HDLC processor (13) through a synchronous pseudo-TDM interface (14) in which the HDLC channels are multiplexed in time and vice versa in the opposite direction. In one direction the algorithm is based on the writing of the HDLC channels in a dedicated buffer (17) and in reading these buffers with a common synchronous clock just above the expected maximum HDLC rate. The under-run condition is avoided by inserting neutral information between the end byte and the start byte of the HDLC packets when this is suggested by the buffer fill monitoring function. A simple function to locate the first and last bytes of each HDLC packet read by the buffer is hence used in combination with the buffer fill monitoring function. The algorithm is also suited in the opposite direction in which different asynchronous physical lines receive their HDLC channels from a synchronous TDM-type interface on condition that this interface clock domain be just below the minimum expected HDLC output rate. In this case also the under-run conditions are avoided by insertion of neutral data after having used the same algorithm described above. Adaptation devices and a telecommunications card using them are also proposed.
    • 一种用于将一定数量的异步HDLC信道(15)的速率适应于适合于通过HDLC信道被多路复用的同步伪TDM接口(14)与HDLC处理器(13)进行接口的单个​​时钟域的方法 时间,反之亦然。 在一个方向上,算法基于在专用缓冲​​器(17)中写入HDLC通道,并且在正好高于预期最大HDLC速率的公共同步时钟读取这些缓冲器。 当由缓冲区填充监视功能建议时,通过在HDLC数据包的结束字节和起始字节之间插入中性信息来避免运行不足的情况。 因此,缓冲区读取的每个HDLC包的第一个和最后一个字节的简单功能与缓冲区填充监视功能结合使用。 该算法也适用于不同异步物理线路从同步TDM类型接口接收其HDLC信道的相反方向,条件是该接口时钟域刚好低于最低预期HDLC输出速率。 在这种情况下,也可以通过在使用上述相同的算法之后插入中性数据来避免运行不足的情况。 还提出了适应装置和使用它们的电信卡。