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1. 发明授权

US06876263B1 Dual voltage-controlled oscillator structure with powder-down feature 有权
标题翻译：双压控振荡器结构，具有粉碎功能
公开(公告)号：US06876263B1
公开(公告)日：2005-04-05
申请号：US10382638
申请日：2003-03-05
申请人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
发明人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
IPC分类号： H03B1/00 , H03B27/00
CPC分类号： H03B5/06 , H03B2200/0048
摘要： A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.
摘要翻译：压控振荡器（“VCO”）结构包括多个VCO电路，每个VCO电路具有不同的额定工作频率范围。通过各个VCO电路的选择性激活/去激活来调节VCO结构的功耗。在优选实施例中，在任何给定时间只有一个VCO电路是有效的。可以选择有源VCO以满足特定应用的要求和/或补偿半导体制造工艺变化。

2. 发明授权

US06720818B1 Method and apparatus for maximizing an amplitude of an output signal of a differential multiplexer 失效
标题翻译：用于最大化差分多路复用器的输出信号的幅度的方法和装置
公开(公告)号：US06720818B1
公开(公告)日：2004-04-13
申请号：US10290659
申请日：2002-11-08
申请人： Zhixiang Jason Liu , Shuyu Lei , Harry Huy Dang , Thomas Clark Bryan
发明人： Zhixiang Jason Liu , Shuyu Lei , Harry Huy Dang , Thomas Clark Bryan
IPC分类号： H03K1762
CPC分类号： H03K17/693 , H03K17/005 , H03K2217/0036
摘要： An amplitude of a differential output signal at a differential multiplexer is maximized by presenting, in response to a differential selection signal, a high impedance to each output port of each differential transistor of a non-selected differential transistor pair. A differential input signal is received at each differential transistor pair. Each transistor of each differential transistor pair is connected to a current source through an independent selection transistor. In response to the differential selection signal, each of the selection transistors is placed in an off state resulting in a high impedance between the output ports of the transistors of the non-selected differential transistor pair.
摘要翻译：通过响应于差分选择信号，向未选择的差分晶体管对的每个差分晶体管的每个输出端口呈现高阻抗，使差分多路复用器的差分输出信号的幅度最大化。在每个差分晶体管对接收差分输入信号。每个差分晶体管对的每个晶体管通过独立的选择晶体管连接到电流源。响应于差分选择信号，每个选择晶体管被置于截止状态，从而在未选择的差分晶体管对的晶体管的输出端口之间产生高阻抗。

3. 发明授权

US06552582B1 Source follower for low voltage differential signaling 有权
标题翻译：源极跟随器用于低电压差分信号
公开(公告)号：US06552582B1
公开(公告)日：2003-04-22
申请号：US09966388
申请日：2001-09-27
申请人： Thomas Clark Bryan , Harry Huy Dang
发明人： Thomas Clark Bryan , Harry Huy Dang
IPC分类号： H03B100
CPC分类号： H03K19/018514 , H03K17/6871 , H04L25/0272
摘要： A source follower circuit for low voltage differential signaling (LVDS) has a low power consumption, low noise, and the ability to drive a highly capacitive load at an output port of an integrated circuit (IC). The source follower circuit includes a first p-channel transistor having a drain coupled to a supply voltage and a gate coupled to a first input; a second p-channel transistor having a drain coupled to the supply voltage and a gate coupled to a second input which is complementary to the first input; a third p-channel transistor having a gate coupled to the second input, a source coupled to ground, and a drain coupled to a source of the first p-channel transistor which forms a first output; and a fourth p-channel transistor having a source coupled to the ground and a drain coupled to a source of the second p-channel transistor which forms a second output which is complementary to the first output. Advantageously, the output signals of the circuit are referenced to ground and are less affected by power supply variations.
摘要翻译：用于低电压差分信号（LVDS）的源极跟随器电路具有低功耗，低噪声以及在集成电路（IC）的输出端口处驱动高容性负载的能力。源极跟随器电路包括具有耦合到电源电压的漏极和耦合到第一输入的栅极的第一p沟道晶体管; 具有耦合到所述电源电压的漏极的第二p沟道晶体管和耦合到与所述第一输入互补的第二输入的栅极; 第三p沟道晶体管，其具有耦合到第二输入的栅极，耦合到地的源极和耦合到形成第一输出的第一p沟道晶体管的源极的漏极; 以及第四p沟道晶体管，其具有耦合到地的源极和耦合到第二p沟道晶体管的源极的漏极，其形成与第一输出互补的第二输出。有利地，电路的输出信号参考地，并且受电源变化的影响较小。

4. 发明授权

US06169421A Complementary metal-oxide semiconductor buffer 有权
标题翻译：互补金属氧化物半导体缓冲液
公开(公告)号：US06169421A
公开(公告)日：2001-01-02
申请号：US09303726
申请日：1999-05-03
申请人： Thomas Clark Bryan , Harry Huy Dang
发明人： Thomas Clark Bryan , Harry Huy Dang
IPC分类号： H03K190948
CPC分类号： H03K19/0013
摘要： A CMOS buffer for interfacing TTL-standard signals and capable of driving a high capacitance load such as a transmission line with low switching noise and low power consumption. The CMOS buffer includes two CMOS branch circuits that control the operation of a CMOS output device. Each branch circuit includes a first delay and a second delay greater than the first delay. The CMOS output device includes a complementary pair of MOS transistors. The first MOS transistor of the CMOS output device is operated by the first branch circuit in response to a signal that is delayed by the first or the second delay. The second MOS transistor of the CMOS output device is operated by the second branch circuit in response to delay of the signal by the second or the first delay.
摘要翻译：用于连接TTL标准信号并能够驱动高电容负载的CMOS缓冲器，例如具有低开关噪声和低功耗的传输线。 CMOS缓冲器包括两个CMOS分支电路，用于控制CMOS输出设备的工作。每个分支电路包括大于第一延迟的第一延迟和第二延迟。 CMOS输出装置包括一对互补的MOS晶体管。 CMOS输出装置的第一MOS晶体管响应于延迟了第一或第二延迟的信号由第一分支电路操作。 CMOS输出装置的第二MOS晶体管响应于第二或第一延迟的信号延迟由第二分支电路操作。

5. 发明授权

US5955924A Differential metal-oxide semiconductor (CMOS) push-pull buffer 失效
标题翻译：差分金属氧化物半导体（MOS）推挽式缓冲器
公开(公告)号：US5955924A
公开(公告)日：1999-09-21
申请号：US63528
申请日：1998-04-21
申请人： Thomas Clark Bryan , Harry Huy Dang
发明人： Thomas Clark Bryan , Harry Huy Dang
IPC分类号： H03F3/18 , H03F3/45 , H03F3/26
CPC分类号： H03F3/45076
摘要： A differential cMOS push-pull buffer includes a pair of push-pull sections, a cMOS current source transistor connected to the push-pull sections for providing current thereto, and two cMOS trickle current transistors, each connected to an output node of a respective push-pull section for conducting a trickle current at the output node. In each push-pull section a trickle current enhances the speed of operation, thereby maintaining desirable attributes in output waveforms.
摘要翻译：差分cMOS推挽缓冲器包括一对推挽部分，连接到用于提供电流的推挽部分的cMOS电流源晶体管和两个cMOS涓流电流晶体管，每个连接到相应推挽的输出节点 - 用于在输出节点处进行涓流电流的 - 空间部分。在每个推挽部分中，涓流电流增加了操作速度，从而在输出波形中保持期望的属性。

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