专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08111785B2 Auto frequency acquisition maintenance in a clock and data recovery device 有权
标题翻译：自动频率采集维护在时钟和数据恢复设备中
公开(公告)号：US08111785B2
公开(公告)日：2012-02-07
申请号：US12372946
申请日：2009-02-18
申请人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
发明人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
IPC分类号： H03D3/18 , H03D3/24 , H04L7/00
CPC分类号： H04L7/0331 , H03L7/0891 , H03L7/095 , H03L7/113 , H03L7/1976 , H04L7/0004
摘要： A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.
摘要翻译：提供了一种用于时钟和数据恢复（CDR）设备中的自动频率采集维护的系统和方法。在自动频率采集（AFA）模式中，该方法使用相位检测器（PHD）来获取具有初始第一频率的非同步输入通信信号的相位。在信号失去锁定/丢失（LOL / LOS）信号被断言的情况下，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生合成信号。响应于使用PFD产生合成信号并且LOL / LOS信号被无效，旋转频率检测器（RFD）用于产生具有等于输入通信信号频率的频率的合成信号。随着LOL / LOS信号的持续消除，PHD被使能，并且获取输入信号的相位。

2. 发明申请

US20090147904A1 Frequency Lock Stability in Device Using Overlapping VCO Bands 有权
标题翻译：使用重叠VCO频带的设备中的频率锁定稳定性
公开(公告)号：US20090147904A1
公开(公告)日：2009-06-11
申请号：US12388024
申请日：2009-02-18
申请人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
发明人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H03L7/0891 , H03L7/113 , H03L7/1976 , H04L7/033
摘要： A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.
摘要翻译：提供了一种用于使用重叠压控振荡器（VCO）频带的接收机中的频率锁定稳定性的系统和方法。接受输入通信信号并选择初始VCO。使用锁相环（PLL）和初始VCO，获取输入通信信号的频率，并测量初始VCO的采集信号调谐电压。然后，初始VCO被分离并且多个相邻频带VCO被顺序地接合。测量每个VCO的获取的信号调谐电压，并且选择能够使用最接近预定调谐电压范围的中点的获取的信号调谐电压来产生输入通信信号频率的最终VCO。

3. 发明申请

US20090122935A1 False frequency lock detector 有权
标题翻译：虚拟锁定检测器
公开(公告)号：US20090122935A1
公开(公告)日：2009-05-14
申请号：US11983675
申请日：2007-11-09
申请人： Simon Pang , Viet Linh Do , Mehmet Mustafa Eker
发明人： Simon Pang , Viet Linh Do , Mehmet Mustafa Eker
IPC分类号： H04L7/02
CPC分类号： H04L7/0083 , H03L7/095 , H03L2207/14 , Y10S331/02
摘要： A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.
摘要翻译：提供了用于检测时钟和数据恢复（CDR）设备中的假时钟频率锁定的系统和方法。该方法以第一速率接收数字原始数据信号，并计算原始数据信号中的边沿转换，创建原始计数。时钟信号也以第二速率被接受。时钟信号是从原始数据信号恢复的定时参考。原始数据信号以响应于时钟信号的速率被采样，产生采样信号。在采样信号中计数边沿转换，创建采样计数。然后，将原始计数与采样计数进行比较，以确定第一速率是否等于第二速率。该方法用于确定第二速率是否小于第一速率 - 以检测时钟信号是否被错误地锁定到第一速率。

4. 发明申请

US20080112525A1 System and method for automatic clock frequency acquisition 有权
标题翻译：自动时钟频率采集的系统和方法
公开(公告)号：US20080112525A1
公开(公告)日：2008-05-15
申请号：US11595012
申请日：2006-11-09
申请人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
发明人： Viet Linh Do , Mehmet Mustafa Eker , Simon Pang
IPC分类号： H03D3/24
CPC分类号： H03L7/113 , H03L7/093 , H03L7/0995 , H03L7/1974 , H04L7/033 , H04L7/0331
摘要： A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer ≧1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1=Fref1/(x−1).
摘要翻译：提供了一种用于自动获取串行数据流时钟的系统和方法。该方法接收到具有未知时钟频率的串行数据流，并粗略地确定时钟频率。通过（最初）选择高频第一参考时钟（Fref 1）粗略地确定频率，并且以等于Fref 1 / n的多个采样频率对串行数据流的第一时间段中的数据转换次数进行计数，其中n是整数> = 1。将每个采样频率的计数与Fref 1（n = 1）的计数进行比较。接下来，确定最高采样频率（n = x），其具有比Fref 1更低的计数，并且粗略时钟频率被设置为Fc 1 = Fref 1 /（x-1）。

5. 发明申请

US20080304610A1 Frequency Reacquisition in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的频率重新采集
公开(公告)号：US20080304610A1
公开(公告)日：2008-12-11
申请号：US12194744
申请日：2008-08-20
申请人： Viet Linh Do , Mehmet Mustafa Eker
发明人： Viet Linh Do , Mehmet Mustafa Eker
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03L7/081 , H03L7/113 , H03L7/18 , H03L7/1976
摘要： A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中重新获取非同步通信信号的系统和方法。该方法最初获取具有输入数据频率的非同步通信信号的相位。响应于获取输入数据频率的相位，产生具有输出频率的合成信号。另外，作为获取输入数据频率的结果，选择频率比值。将输出频率除以所选择的频率比值，产生具有除数频率的除数信号，与参考信号频率进行比较。响应于比较，频率比值被保存在有形存储介质中。响应于通信信号丢失相位锁定，从存储器检索频率比值。获取输入数据频率后，重新获取通信信号的相位。

6. 发明授权

US08094754B2 Frequency hold mechanism in a clock and data recovery device 有权
标题翻译：时钟和数据恢复设备中的频率保持机制
公开(公告)号：US08094754B2
公开(公告)日：2012-01-10
申请号：US12327776
申请日：2008-12-03
申请人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
发明人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
IPC分类号： H03D3/24
CPC分类号： H04L7/033 , H03L7/087 , H03L7/10 , H03L7/1976 , H03L7/22
摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

7. 发明申请

US20090147901A1 Auto Frequency Acquisition Maintenance in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的自动采集维护
公开(公告)号：US20090147901A1
公开(公告)日：2009-06-11
申请号：US12372946
申请日：2009-02-18
申请人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
发明人： Viet Linh Do , Philip Michael Clovis , Michael Hellmer , Mehmet Mustafa Eker , Hongming An , Simon Pang
IPC分类号： H04L7/00
CPC分类号： H04L7/0331 , H03L7/0891 , H03L7/095 , H03L7/113 , H03L7/1976 , H04L7/0004
摘要： A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.
摘要翻译：提供了一种用于时钟和数据恢复（CDR）设备中的自动频率采集维护的系统和方法。在自动频率采集（AFA）模式中，该方法使用相位检测器（PHD）来获取具有初始第一频率的非同步输入通信信号的相位。在信号失去锁定/丢失（LOL / LOS）信号被断言的情况下，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生合成信号。响应于使用PFD产生合成信号并且LOL / LOS信号被无效，旋转频率检测器（RFD）用于产生具有等于输入通信信号频率的频率的合成信号。随着LOL / LOS信号的持续消除，PHD被使能，并且获取输入信号的相位。

8. 发明申请

US20090092213A1 Frequency Hold Mechanism in a Clock and Data Recovery Device 有权
标题翻译：时钟和数据恢复设备中的频率保持机制
公开(公告)号：US20090092213A1
公开(公告)日：2009-04-09
申请号：US12327776
申请日：2008-12-03
申请人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
发明人： Mehmet Mustafa Eker , Simon Pang , Viet Linh Do , Hongming An , Philip Michael Clovis
IPC分类号： H04L7/04
CPC分类号： H04L7/033 , H03L7/087 , H03L7/10 , H03L7/1976 , H03L7/22
摘要： A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.
摘要翻译：提供了一种用于在时钟和数据恢复（CDR）设备频率合成器中保持非同步通信信号的频率的系统和方法。该方法最初获取具有第一频率的非同步第一通信信号的相位，并且将第一合成信号除以所选频率比值，产生频率等于参考信号频率的频率检测信号。响应于丢失第一通信信号并随后接收具有非预定第二频率的第二通信信号，基于第二频率相同或接近第一频率的假设，从存储器检索频率比值。使用相位频率检测器（PFD），参考信号和频率比值，产生具有等于第一频率的输出频率的第二合成信号。使用旋转频率检测器（RFD），第二通信信号和第二合成信号，生成具有等于第二频率的输出频率的第二合成信号。

9. 发明授权

US06876263B1 Dual voltage-controlled oscillator structure with powder-down feature 有权
标题翻译：双压控振荡器结构，具有粉碎功能
公开(公告)号：US06876263B1
公开(公告)日：2005-04-05
申请号：US10382638
申请日：2003-03-05
申请人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
发明人： Wei Li , Thomas Clark Bryan , Harry Huy Dang , Mehmet Mustafa Eker
IPC分类号： H03B1/00 , H03B27/00
CPC分类号： H03B5/06 , H03B2200/0048
摘要： A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.
摘要翻译：压控振荡器（“VCO”）结构包括多个VCO电路，每个VCO电路具有不同的额定工作频率范围。通过各个VCO电路的选择性激活/去激活来调节VCO结构的功耗。在优选实施例中，在任何给定时间只有一个VCO电路是有效的。可以选择有源VCO以满足特定应用的要求和/或补偿半导体制造工艺变化。

10. 发明授权

US06566967B1 Configurable triple phase-locked loop circuit and method 有权
标题翻译：可配置三相锁相环电路及方法
公开(公告)号：US06566967B1
公开(公告)日：2003-05-20
申请号：US10085458
申请日：2002-02-26
申请人： Sudhaker Reddy Anumula , Joseph J. Balardeta , Wei Fu , Paul Vanderbilt , Mehmet Mustafa Eker
发明人： Sudhaker Reddy Anumula , Joseph J. Balardeta , Wei Fu , Paul Vanderbilt , Mehmet Mustafa Eker
IPC分类号： H03L700
CPC分类号： H03L7/18 , H03L7/087 , H03L7/0891 , H03L7/107 , H03L7/113 , H03L7/14
摘要： A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.
摘要翻译：具有多个检测元件的可配置PLL架构。可配置PLL电路包括用于提供第一差分信号的第一检测器，用于提供第二差分信号的第二检测器，用于提供第三差分信号的第三检测器，以及用于使第一，第二和第第三检测器。 PLL电路还包括多路复用器，用于从相应的使能检测器接收至少一个差分信号，并提供多路复用的差分信号输出。在操作中，选择操作模式，并且启用一个或多个检测器以使用一个或多个输入参考信号进行操作。使能的检测器的输出由多路复用器接收以完成所选择的操作模式的操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式